System to set burst mode in a device
AssigneeFujitsu Limited
InventorTakao Akaogi
Life of this patent
Estimating the term…
Abstract
System to set burst mode in a memory device. The system includes apparatus having a first signal buffer that receives an address control signal and produces a buffered address control signal. A mode detection circuit is included that receives the buffered address control signal and produces a burst control signal. The apparatus also includes a core access trigger circuit that receives the burst control signal and generates a core access signal that is used to begin a core access for burst mode operation of the memory.
Claims6
Apparatus to set burst mode operation in a memory device, the apparatus comprising:
- a first signal buffer that receives an address control signal and produces a buffered address control signal;
- a mode detection circuit that receives the buffered address control signal and a system clock signal and produces a burst control signal, the burst control signal generated if the system clock signal is activated during a time when the buffered address control signal is active;
- and
- a core access trigger circuit that receives the burst control signal and generates a core access signal that is used to begin a next core access for burst mode operation of the memory,
- wherein if said burst control signal is activated outside a core access period, said core access signal is generated when said burst control signal is activated, if said burst control signal is activated within the core access period, said core access signal is generated when said core access finishes.
A method for setting a burst mode in a memory device, the method comprising steps of:
- receiving an address control signal to produce a buffered address control signal;
- producing a burst control signal from the buffered address control signal and a system clock, wherein the burst control signal generated if the system clock signal is activated during a time when the buffered address control signal is active;
- and
- generating a core access signal from the burst control signal, the core access signal is used to begin a next core access for burst mode operation of the memory,
- wherein if said burst control signal is activated outside a core access period, said core access signal is generated when said burst control signal is activated, if said curst control signal is activated within the core access period, said core access signal is generated when said core access finishes.
Dependencies are inferred from the claim text.