US 6,587,390 B1 · Memory controller for handling data transfers which exceed the page width of DDR SDRAM devices

Abstract

A memory controller includes a pair of input command decoders and a pair of multiplexers. If the memory controller receives a data transfer request related to a read or write burst which will stay within a page of memory, the first input command decoder circuit generates a first input command which is then passed, in sequence, by the first and second multiplexers. Conversely, if the data transfer request relates to a read or write burst which will burst over a page of the memory, the second input command decoder circuit generates second and third input commands. The second input command passes through the second multiplexer circuit while the third input command is held in a command register. The third input command is subsequently passed through the first and second multiplexers.

Claims16

Dependent claims

A computer system, comprising:

a processor;
a memory;
and
a memory controller having a first side coupled to said processor and a second side coupled to said memory, said memory controller comprising:
a first decoder circuit coupled between said first and second sides of said memory controller, said first decoder circuit generating a first input command for executing a data transfer request to/from said memory if said data transfer request relates to a data transfer sized at or below a threshold value;
and
a second decoder circuit coupled between said first and second sides of said memory controller, said second decoder circuit generating second and third input commands for executing said data transfer request to/from said memory if said data transfer request relates to a data transfer sized above said threshold value.

4 more elements

A memory subsystem for an electronic device, said memory subsystem comprising:

at least one memory chip;
and
a memory controller for controlling accesses to said at least one memory chip, said memory controller comprising:
a first decoder circuit having input and output sides;
a second decoder circuit having input and output sides, said input side of said second decoder circuit coupled to said input side of said first decoder circuit;
a multiplexer circuit having input and output sides, said input side of said multiplexer circuit coupled to said output sides of said first and second decoder circuits and said output side of said multiplexer circuit coupled to said at least one memory chip;
said multiplexer circuit configured to selectively pass a first input command, generated by said first decoder circuit, for executing a data transfer request if said memory controller is to control a data transfer sized at or below a threshold value or second and third input commands, generated by said second decoder circuit, for executing said data transfer request if said memory controller is to control a data transfer sized above said threshold value.

4 more elements

A memory controller, comprising:

a first decoder circuit having input and output sides;
a second decoder circuit having input and output sides, said input side of said second decoder circuit coupled to said input side of said first decoder circuit;
a multiplexer circuit having input and output sides, said input side of said multiplexer circuit coupled to said output sides of said first and second decoder circuits;
said multiplexer circuit configured to selectively pass a first input command generated by said first decoder circuit if said memory controller is to control a data transfer sized at or below a threshold value or second and third input commands generated by said second decoder circuit if said memory controller is to control a data transfer sized above said threshold value.

1 more element

Dependencies are inferred from the claim text.

Memory controller for handling data transfers which exceed the page width of DDR SDRAM devices

Life of this patent

Memory controller for handling data transfers which exceed the page width of DDR SDRAM devices

Life of this patent

Abstract

Claims16