Method and apparatus for reducing write operation time in dynamic random access memories

A method for reducing the write time for a dynamic random access memory (DRAM) cell, the cell including a data bit storage element for storing a data bit at a logic 0 voltage level or at a logic 1 voltage level, the method comprising:

• receiving a write command from a controller;
• responsive to said write command, creating a preset voltage level within the cell, said preset voltage level having an intermediate value between the logic 0 voltage level and the logic 1 voltage level;
• and
• coupling the cell to a write signal;
• wherein said write signal, when coupled to the cell, drives the cell voltage from said preset voltage level to either the logic 0 voltage level or the logic 1 voltage level.

A computer memory system, comprising:

• a dynamic random access memory (DRAM) cell, the cell including a data bit storage element for storing a data bit at a logic 0 voltage level or at a logic 1 voltage level;
• a controller, said controller generating a write command for said cell;
• said cell, responsive to said write command from said controller, having a preset cell voltage therein, said cell voltage being at an intermediate voltage level between said logic 0 voltage level and said logic 1 voltage level;
• and
• a write signal, coupled to said cell;
• wherein when said write signal is coupled to said cell, the cell voltage is driven from said intermediate voltage level to either said logic 0 voltage level or said logic 1 voltage level.