Semiconductor memory having multiple redundant columns with offset segmentation boundaries
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
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Abstract
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.
Claims7
A method of repairing a memory device comprising:
- applying a programming signal to a memory device, said memory device including a bank of memory cells, said memory cells each arranged in one of a first plurality of columns and a second plurality of redundant columns, each column of said first plurality and redundant column of said second plurality respectively having a respective first end adjacent to an edge of said bank;
- programming a first segmentation boundary into a first one of said second plurality of redundant columns at a first distance from said respective first end;
- and
- programming a second segmentation boundary into a second one of said second plurality of redundant columns at a second distance from said respective first end, wherein said first and second distances differ from one another.
A method of substituting a redundant memory device for a failed memory device comprising:
- programming a first segmentation boundary into a first redundant column of a memory device and a second segmentation boundary into said first redundant column so as to define a first segment and a second segment, said first segment including a first contiguous plurality of cells, said second segment including a second plurality of cells and a third plurality of cells, said second and third pluralities of cells being non-contiguous with respect to one another.
A memory device comprising:
- a first plurality of memory cells, said first plurality of memory cells arranged in a second plurality of row-blocks within a third plurality of columns;
- a fourth plurality of redundant memory cells, said fourth plurality of redundant memory cells arranged in a fifth plurality of segments within a sixth plurality of redundant columns, each segment of said fifth plurality of segments including a respective first and second segmentation boundary at respective first and second ends thereof;
- and
- a programming circuit for setting respective first and second locations of said respective first and second segmentation boundaries of each segment of said fifth plurality of segments, said programming circuit adapted to define said respective first and second locations within a first redundant column of said sixth plurality of redundant columns to be misaligned with respect to the respective first and second locations within a second adjacent redundant column of said sixth plurality of redundant columns.
Dependencies are inferred from the claim text.