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US 6,587,385 B2Granted
Clock synchronous semiconductor memory device having a reduced access time
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTsukasa Ooishi
Life of this patent
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Abstract
In successively executed operations modes in a synchronous semiconductor memory device, data access time after the application of a row access command is reduced by providing a plurality of control signal lines, such as a differential pair of sense amplifier enable lines, advantageously shorting the control lines, and then driving the control lines to a predetermined voltage level after the elapse of a prescribed time period.
Claims10
A semiconductor device comprising:
- a plurality of control signal lines each for transmitting a control signal for controlling a predetermined operation;
- and
- control circuitry for electrically shorting at least two control signal lines of said plurality of control signal lines for a predetermined time period upon starting said predetermined operation, said at least two control signal lines each transmitting its respective control signal to a control gate of a transistor performing said predetermined operation.
Dependencies are inferred from the claim text.