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US 6,587,384 B2Granted
Multi-function serial I/O circuit
AssigneeHewlett-Packard Development Company, L.P.
InventorFrederick A Perner
Life of this patent
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Abstract
An input/output (I/O) circuit of a memory device performs I/O and stores data for write-backs. The write-back data may be used for destructive read operations. The I/O circuit may also be configured to perform data balancing, write-verifies and built-in self test (BIST).
Claims24
An input/output circuit comprising:
- a first register having a first input and first output;
- a second register having a second input coupled to the first output;
- and
- a third register having a third input coupled to the first output, wherein the third register is directly responsive to the first output of the first register.
1 more element
An I/O circuit for a memory device, the circuit comprising:
- a first register having a first input and a first output;
- a second register having a second input;
- a first transmission gate for coupling the first output to the second input;
- a third register having a third input;
- a second transmission gate for coupling the first output to the third input;
- and
- a control for causing the first transmission gate to shift an output of the first register into the second register during a first mode of operation, causing the second transmission gate to shift the output of the first register into the third register during a second mode of operation, and for causing the second transmission gate to isolate the third register during a third mode of operation.
4 more elements
A random access memory device comprising:
- an array of memory cells;
- a plurality of drivers, each driver corresponding to a slice of the memory cells;
- a plurality of sense amplifiers, each sense amplifier corresponding to a slice of the memory cells;
- and
- a plurality of I/O circuits, each I/O circuit corresponding to a slice of the memory cells, each I/O circuit including a first register having a first output and a first input coupled to an output of the corresponding sense amplifier, a second register having a second input coupled to the first output, and a third register having a third input coupled to the first output such that the third register is directly responsive to the first output of the first register, the third register having a third output coupled to an input of the corresponding driver.
2 more elements
A data storage device comprising:
- an array of memory cells;
- a plurality of sense amplifiers, each sense amplifier corresponding to a slice of the memory cells;
- a plurality of I/O circuits, each I/O circuit corresponding to a slice of the memory cells, each I/O circuit including a first register having a first output and a first input coupled to an output of the corresponding sense amplifier, a second register having a second input coupled to the first output, and a third register having a third input coupled to the first output of the first register, and
- a controller for controlling the I/O circuits to perform at least one of data balancing, write-verify, built-in self test, and write-back.
1 more element
Dependencies are inferred from the claim text.