Erase block architecture for non-volatile memory
AssigneeMicron Technology, Inc.
InventorsFrankie Fariborz Roohparvar, Kevin C. Widmer
Life of this patent
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Abstract
A flash memory has erase blocks aligned primarily with array rows and secondarily with array rows. This architecture allows data to be stored across numerous pages without risking accidental erasure caused by crossing multiple erase blocks. As a result, non-volatile memory devices to be more easily substituted for volatile memory devices. In one embodiment, a flash memory includes an array of memory cells that have a plurality of adjacent pages. Addresses of the memory cells are scrambled within the pages to define erase blocks that cross the page boundaries.
Claims19
A non-volatile memory device comprising:
- an array of memory cells arranged in rows and columns;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
A non-volatile memory comprising:
- an array of memory cells arranged in rows and columns;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- and
- erase circuitry to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages.
A flash memory device comprising:
- an array of floating gate memory cells arranged in rows and columns;
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array;
- erase circuitry to erase blocks of the array, wherein the blocks are aligned with the memory array rows such that they cross the plurality of pages;
- and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled such that each erase block contains linear addresses.
A processing system comprising:
- a processor;
- and
- a non-volatile memory coupled to communicate with the processor, the nonvolatile memory comprises,
- an array of memory cells arranged in rows and columns,
- sense circuitry comprising a plurality of sense amplifier groups coupled to the array columns, wherein each group of sense amplifiers defines a page of the memory array, and
- addressing circuitry to access the array, wherein addresses of the memory cells are scrambled to define erase blocks that cross the plurality of pages.
A method of operating a non-volatile memory device comprising:
- storing data in a plurality of adjacent array pages sharing common row addresses;
- and
- erasing a block of memory cells, wherein the block comprises columns of memory cells located in the plurality of pages.
Dependencies are inferred from the claim text.