Programming method for non-volatile semiconductor memory device
AssigneesHalo LSI Design & Device Technology, Inc., Seiko Epson Corporation
InventorsMasahiro Kanai, Teruhiko Kamei
Life of this patent
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Abstract
A method is provided for programming data for a memory element of a twin memory cell (i). The word line WL1 is set to a programming word line selection voltage, the control gate CG[i+1] is set to a programming control gate voltage, and the control gate CG[i] is set to an over-ride voltage. The bit line BL[i+1] is set to a programming bit line voltage, and the bit line BL[i+2] is set to Vdd, but not to 0 V.
Claims10
A programming method for a non-volatile semiconductor memory device in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−1), (i), and (i+1) whose word gates are connected to one word line, data for the second non-volatile memory element of the twin memory cell (i) is programmed, said method comprising:
- setting the word line to a programming word line selection voltage;
- setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to a programming control gate voltage;
- setting the second control gate of the twin memory cell (i−1) and the first control gate of the twin memory cell (i) to an over-ride voltage;
- setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i) and the first non-volatile memory element of the twin memory cell (i+1) to a programming bit line voltage;
- and
- setting a bit line connected to the second non-volatile memory element of the twin memory cell (i+1) to a voltage higher than 0 V.
A programming method for a non-volatile semiconductor memory device in which a plurality of twin memory cells, each having one word gate and first and second non-volatile memory elements controlled by first and second control gates, are arranged and, from among three adjacent twin memory cells (i−1), (i) and (i+1) whose word gates are connected to one word line, data for the first non-volatile memory element of the twin memory cell (i) is programmed, said method comprising:
- setting the word line to a programming word line selection voltage;
- setting the second control gate of the twin memory cell (i−1) and the first control gate of the twin memory cell (i) to a programming control gate voltage;
- setting the second control gate of the twin memory cell (i) and the first control gate of the twin memory cell (i+1) to an over-ride voltage;
- setting a bit line commonly connected to the second non-volatile memory element of the twin memory cell (i−1) and the first non-volatile memory element of the twin memory cell (i) to a programming bit line voltage;
- and
- setting a bit line connected to the first non-volatile memory element of the twin memory cell (i−1) to a voltage higher than 0 V.
Dependencies are inferred from the claim text.