Apparatus and method for refreshing a flash memory unit

A Flash memory unit comprising:

• a plurality of Flash memory cells, each Flash memory cell including a source, a drain, a well, a floating gate, and a control gate,
• a dummy Flash memory cell, each dummy Flash memory cell including a source, a drain, a well, a floating gate, and a control gate,
• a comparison circuit for comparing the current through the dummy Flash memory cell with the current through one of the Flash memory cells,
• a control circuit for controlling when the current through the Flash memory cell represents a predetermined amount of charge stored on the floating gate of the Flash memory cell;
• and
• a state machine, the state machine controlling the control circuit, the control circuit thereby determining the identification of a logic state identified by a NORMAL READ operation and the logic state identified by a TEST READ operation.

Apparatus for testing a Flash memory cell, the apparatus comprising:

• a dummy memory cell;
• a component for generating a first voltage proportional to current through the dummy cell;
• a component for generating a second voltage proportional to the current through the Flash memory cell, wherein the factor of proportionality between the second voltage and the current through the Flash memory cell is controllable;
• and
• voltage supply units for activating the dummy cell and the Flash memory cell;
• wherein a first factor of proportionality tests the Flash memory cell for a NORMAL READ operation, and wherein a second factor of proportionality tests the Flash memory unit for a TEST READ operation.