Nonvolatile semiconductor memory device with reliable verify operation

A nonvolatile semiconductor memory device, comprising:

• a plurality of reference cell transistors connected together and receiving a common gate voltage;
• a signal line having an electric current running therethrough that is a composite of electric currents running through the reference cell transistors in accordance with the gate voltage;
• a comparison circuit which compares the electric current running through the signal line with an electric current corresponding to data of a memory cell.

A method of adjusting a voltage versus current characteristic in a nonvolatile semiconductor memory device which includes a first reference cell transistor, a second reference cell transistor connected in series to the first reference cell transistor, and a third reference cell transistor connected in parallel to the series connection of the first reference cell transistor and the second reference cell transistor, wherein a common gate voltage is applied to gates of the first through third reference cell transistors, and an electric current corresponding to data of a memory cell is compared with an electric current that is a sum of an electric current running through the series connection and an electric current running through the third reference cell transistor, said method comprising:

• setting threshold voltage levels Vt0, Vt1, and Vt2 of the first, second, and third respective reference cell transistors such that Vt1<Vt0<Vt2;
• and
• adjusting one of the threshold voltage levels Vt1 and Vt2 while maintaining Vt1<Vt0<Vt2, thereby adjusting a slope of a voltage versus current characteristic defined by the gate voltage and the electric current that is said sum.

A method of adjusting a voltage versus current characteristic in a nonvolatile semiconductor memory device which includes a first reference cell transistor, a second reference cell transistor connected in series to the first reference cell transistor, and a third reference cell transistor connected in parallel to the first reference cell transistor, wherein a common gate voltage is applied to gates of the first through third reference cell transistors, and an electric current corresponding to data of a memory cell is compared with an electric current running through the second reference cell transistor, said method comprising:

• setting threshold voltage levels Vt0, Vt1, and Vt2 of the first, second, and third respective reference cell transistors such that Vt1<Vt0<Vt2;
• and
• adjusting one of the threshold voltage levels Vt1 and Vt2 while maintaining Vt1<Vt0<Vt2, thereby adjusting a slope of a voltage versus current characteristic defined by the gate voltage and the electric current running through the second reference cell transistor.