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US 6,587,376 B2Granted
Flash memory cell for high efficiency programming
AssigneeMicron Technology, Inc.
InventorsAndrei Mihnea, Paul J. Rudeck, Chun Chen
Life of this patent
Estimating the term…
Abstract
A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.
Claims33
A flash memory cell comprising:
- a source having an arsenic doped region, the source being surrounded by a heavily doped p-type region;
- a drain;
- a channel coupling the source and drain;
- and
- a control gate located above the channel, wherein the flash memory cell is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source and generating a voltage of more than about four volts across a depletion region in the channel.
2 more elements
A flash memory comprising:
- a source having an arsenic doped region, the source being surrounded by a heavily doped boron region;
- a drain;
- a channel coupling the source and drain;
- and
- a control gate located above the channel, wherein the flash memory is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source and generating a voltage of more than about four volts across a depletion region in the channel.
2 more elements
A flash memory comprising:
- a source surrounded by a heavily doped boron region;
- a drain having an arsenic region surrounded by a phosphorous doped region, the drain abutting a lightly doped boron region;
- a channel extending between the source and drain;
- and
- a control gate located above the channel, wherein the flash memory is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source and generating a voltage of more than about four volts across a depletion region in the channel region.
2 more elements
A flash memory comprising:
- a source having a heavily doped arsenic region, the source surrounded by a heavily doped boron region;
- a drain having a heavily doped arsenic region surrounded by a phosphorous doped region, the drain abutting a lightly doped boron region;
- a channel having a surface, the surface extending from the source to the drain, the channel having a lightly doped boron channel region extending from the surface;
- and
- a control gate formed in a common substrate with the source, the drain, and the channel, wherein the flash memory is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source, and generating a voltage of more than about four volts across a depletion region in the channel.
2 more elements
A flash memory comprising:
- a source having an arsenic doped region, the source being surrounded by a heavily doped p-type region;
- a drain;
- a channel having a surface, the surface extending from the source to the drain, the channel having a heavily boron doped buried channel separated from the surface by a lightly doped boron region;
- and
- a control gate located above the channel, wherein the flash memory is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source and generating a voltage of more than about four volts across a depletion region in the channel.
2 more elements
A flash memory comprising:
- a source;
- a drain having a heavily doped arsenic region surrounded by a phosphorous doped region, the drain abutting a lightly doped boron region;
- a channel having a surface, the surface extending from the source to the drain, the channel having a heavily boron doped buried channel separated from the surface by a lightly doped boron region;
- and
- a stack, the stack formed in a common substrate with the source, the drain, and the channel, the stack having a control gate, a gate dielectric, a floating gate, and an oxide layer, the stack located above the channel, wherein the flash memory is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source, and generating a voltage of more than about four volts across a depletion region in the channel.
2 more elements
A system comprising:
- a processor;
- and
- a memory coupled to the processor, the memory having a plurality of flash memory cells, each of the plurality of flash memory cells having:
- a source having an arsenic doped region, the source being surrounded by a heavily doped boron region;
- a drain;
- a channel having a surface, the surface extending from the source to the drain, the channel having a lightly doped boron channel region extending from the surface;
- and
- a control gate located above the channel, wherein the flash memory cell is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source of each of the plurality of flash memory cells, and generating a voltage of more than about four volts across a depletion region in the channel of each of the plurality of flash memory cells programs each of the plurality of flash memory cells.
5 more elements
A system comprising:
- a processor;
- and
- a memory coupled to the processor, the memory having a plurality of flash memory cells, each of the plurality of flash memory cells having:
- a source having an arsenic doped region, the source being surrounded by a heavily doped boron region;
- a drain;
- a channel having a surface extending between the source and drain, the channel having a heavily boron doped buried channel separated from the surface by a lightly doped boron region;
- and
- a control gate located above the channel, wherein the flash memory cell is programmed by applying a voltage between about 1 volt and about 2.5 volts to the source of each of the plurality of flash memory cells, and generating a voltage of more than about four volts across a depletion region in the channel of each of the plurality of flash memory cells programs each of the plurality of flash memory cells.
5 more elements
Dependencies are inferred from the claim text.