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US 6,587,374 B2Granted
Serial storage device
AssigneeRohm Co., Ltd.
InventorsHiroki Takagi, Yoshihiro Tada, Noriaki Katsuhara
Life of this patent
Estimating the term…
Abstract
Memory cells of a storage device are addressed in n-bit word(s). Each of the n-bit word memory cells are partitioned into k (k≧2) groups of n/k bits. The memory cells are sequentially selected in n/k bits. Data of the selected n/k bit memory cells are read by n/k sense amplifiers and serially output from the storage device as readout data. The storage device requires much less chip area for n/k sense amplifiers and reduced peak currents in a read operation.
Claims4
A serial storage device, comprising:
- at least one memory cell array addressable in multiple n-bit memory cells:
- selection means for partitioning said n-bit memory cells into k (k≧2) groups of n/k-bit memory cells and for selecting said n/k-bit memory cell groups in sequence:
- n/k sense amplifiers for determining the data retrieved from the n/k-memory cells selected by said selection means;
- and
- a register for parallelly receiving the outputs of said sense amplifiers and for serially outputting them as readout data, and
- adapted to perform cell addressing of the memory cells of said memory cell array by a column selection signal and a row selection signal;
- wherein said selection means includes a first selector for selecting, from the row selected by said row selection signal, n-bit memory cells addressed by said column selection signal, and a second selector for partitioning said n-bit memory cells into n/k-bit groups (k≧2) and for sequentially selecting said n/k-bit groups;
- wherein, while said register is serially outputting said readout data, said second selector selects n/k bit data to be output next;
- and
- said n/k sense amplifiers determine said next n/k bit data;
- wherein
- each of said memory cells is an electrically writable and erasable non-volatile memory connected with at least one array source ground line which is common to said n-bit memory cells;
- and
- said n/k memory cells are dispersively distributed with respect to said at least one array source ground line.
11 more elements
A serial storage device, comprising:
- at least one memory cell array addressable in multiple n-bit memory cells:
- selection means for partitioning said n-bit memory cells into k (k≧2) groups of n/k-bit memory cells and for selecting said n/k-bit memory cell groups in sequence:
- n/k sense amplifiers for determining the data retrieved from the n/k-memory cells selected by said selection means;
- and
- a register for parallelly receiving the outputs of said sense amplifiers and for serially outputting them as readout data, and
- adapted to perform cell addressing of the memory cells of said memory cell array by a column selection signal and a row selection signal;
- wherein said selection means includes a first selector for selecting, from the row selected by said row selection signal, n-bit memory cells addressed by said column selection signal, and a second selector for partitioning said n-bit memory cells into n/k-bit groups (k≧2) and for sequentially selecting said n/k-bit groups, and
- further comprising a latch for latching therein n-bit data by sequentially latching externally supplied n/k-bit data in the locations of said latch selected by said second selector, said latch adapted to write said latched n-bit data to said addressed memory cells via said first selector;
- wherein while said register is serially outputting said readout data, said second sector selects n/k bit data to be output next;
- and said n/k sense amplifiers determine said next n/k bit data;
- and
- wherein
- each of said memory cells is an electrically writable and erasable non-volatile memory connected with at least one array source ground line which is common to said n bit memory cells;
- and
- said n/k memory cells are dispersively distributed with respect to said at least one array source ground line.
12 more elements
A serial storage device, comprising:
- at least one memory cell array addressable in multiple n-bit memory cells:
- selection means for partitioning said n-bit memory cells into k (k≧2) groups of n/k-bit memory cells and for selecting said n/k-bit memory cell groups in sequence:
- n/k sense amplifiers for determining the data retrieved from the n/k-memory cells selected by said selection means;
- and
- a register for parallelly receiving the outputs of said sense amplifiers and for serially outputting them as readout data;
- and
- adapted to perform cell addressing of the memory cells of said memory cell array by a column selection signal and a row selection signal
- wherein said selection means is adapted to select, from the row selected by said row selection signal, an n-bit memory cells addressed by said column selection signal to partition said n-bit memory cells into n/k-bit groups (k≧2) and for sequentially selecting said n/k-bit groups;
- wherein, while said register is serially outputting said readout data, said selection means select n/k bit data to be output next;
- and
- said n/k sense amplifiers determine said next n/k bit data;
- and
- wherein
- each of said memory cells is an electrically writable and erasable non-volatile memory connected with at least one array source ground line which is common to said n bit memory cells;
- and
- said n/k memory cells are dispersively distributed with respect to said at least one array source ground line.
13 more elements
A serial storage device, comprising:
- at least one memory cell array addressable in multiple n-bit memory cells:
- selection means for partitioning said n-bit memory cells into k (k≧2) groups of n/k-bit memory cells and for selecting said n/k-bit memory cell groups in sequence:
- n/k sense amplifiers for determining the data retrieved from the n/k-memory cells selected by said selection means;
- and
- a register for parallelly receiving the outputs of said sense amplifiers and for serially outputting them as readout data, and
- adapted to perform cell addressing of the memory cells of said memory cell array by a column selection signal and a row selection signal;
- wherein said selection means is adapted to select, from the row selected by said row selection signal, an n-bit memory cells addressed by said column selection signal to partition said n-bit memory cells into n/k-bit groups (k≧2) and for sequentially selecting said n/k-bit groups;
- further comprising a page buffer for holding externally supplied n/k-bit data in the j word locations of said buffer selected by said selection means, said page buffer adapted to write the whole data in said j word locations to addressed j word memory cells of said memory cell array via said selection means where j≧1;
- wherein, while said register is serially outputting said readout data, said second selector selects n/k bit data to be output next;
- and
- said n/k sense amplifiers determine said next n/k bit data;
- and
- wherein
- each of said memory cells is an electrically writable and erasable non-volatile memory connected with at least one array source ground line which is common to said n bit memory cells;
- and
- said n/k memory cells are dispersively distributed with respect to said at least one array source ground line.
13 more elements
Dependencies are inferred from the claim text.