Memory device having wide margin of data reading operation, for storing data by change in electric resistance value

A memory device comprising:

• a memory array having a plurality of memory cells arranged in a matrix;
• a plurality of read word lines provided in correspondence with rows of said memory cells and selectively activated in accordance with a row selection result in a data reading operation;
• a plurality of bit lines provided in correspondence with columns of said memory cells;
• a plurality of reference voltage lines for supplying a read reference voltage, disposed in correspondence with said columns in the same direction as said plurality of bit lines;
• and
• a data read circuit for supplying a data read current passed to a current path formed between the data read circuit and said read reference voltage to at least one of said plurality of bit lines in accordance with a column selection result,
• each of said plurality of memory cells comprising:
• a memory element whose electric resistance value changes according to a level of storage data;
• and
• a memory selection gate electrically coupled in series with said memory element between corresponding one of said plurality of bit lines and corresponding one of said plurality of reference voltage lines and turned on in response to activation of corresponding one of said plurality of read word lines, and
• in said data reading operation, a sum of the electric resistance value in the reference voltage line corresponding to a selected column and the electric resistance value of the bit line corresponding to the selected column in a portion included in said current path being almost constant independent of said row selection result.