Non-volatile memory circuit

A non-volatile ferroelectric capacitor memory circuit, comprising:

• a word line;
• first and second access transistors having respective gate electrodes coupling with said word line;
• a volatile memory cell portion having a flip-flop configuration and having two internal nodes latched into complementary states during operation of said volatile portion and connected to said first and second access transistors, respectively;
• a first bit line coupling with one of said internal nodes via the source-drain path of said first access transistor;
• a second bit line coupling with second one of said internal nodes via the source-drain path of said second access transistor, whereby said memory circuit is selected when said word line turns on said first and second access transistors thereby to couple said first and second bit lines to said internal nodes, respectively;
• first and second ferroelectric capacitors having respectively first and second plates, wherein said first plates of said first and second ferroelectric capacitors are coupled together to form a common node coupling with one of said two internal nodes;
• a first plate line coupling said second plate of said first ferroelectric capacitor;
• and
• a second plate line coupling said second plate of said second ferroelectric capacitor.