System and method for increasing performance in a compilable read-only memory (ROM)
AssigneeVirage Logic Corporation
InventorsAdam Aleksan Kablanian, Deepak Sabharwal
Life of this patent
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Abstract
A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each memory location is addressable by a row address and a column address. The data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.
Claims21
A technique for increasing performance in a read-only memory (ROM) having at least one input/output (I/O) block, wherein each memory location is addressable by a row address and a column address, said method comprising the steps of:
- providing a predetermined data map to be programmed into said ROM;
- analyzing the number of binary 0's and 1's in a select portion of said ROM under normal addressing;
- interchanging a portion of said row address with a portion of said column address to generate scrambled addresses;
- re-distributing said binary 0's and 1's of said data map using said scrambled addresses and re-analyzing the number of binary 0's and 1's under scrambled addressing;
- and
- selecting one of said normal addressing and said scrambled addressing for programming said ROM depending on which one results in a better distribution of said binary 0's and 1's.
A read-only memory (ROM) for storing a data map, comprising:
- an array of memory locations organized into at least one input/output (I/O) block having a select number of bitlines, said memory locations being addressable by a row address space and a column address space;
- and
- said memory locations having data programmed therein based on a scrambled address scheme, wherein a portion of said row address space is interchanged with a portion of said column address space.
A computer-implemented process for optimizing performance in a read-only memory (ROM) device wherein each memory location is addressable by a row address and a column address, said ROM device operating to contain a data map, comprising the steps of:
- analyzing said data map's distribution of binary 0's and binary 1's in a select portion of said ROM device to determine if said distribution is imbalanced in a normal addressing scheme;
- and
- if said distribution is determined to be imbalanced, scrambling said row address and said column address for memory locations in said select portion to generate scrambled addresses, wherein when said ROM device is programmed in a software environment with said scrambled addresses, said distribution of binary 0's and binary 1's becomes more balanced.
A computer program product having a set of computer-executable instructions for optimizing performance in a read-only memory (ROM) device wherein each memory location is addressable by a row address and a column address, said ROM device operating to contain a data map, comprising:
- program code for analyzing said data map's distribution of binary 0's and binary 1's in a select portion of said ROM device to determine if said distribution is imbalanced in a normal addressing scheme;
- and
- program code for scrambling said row address and said column address for memory locations in said select portion to generate scrambled addresses if said distribution is determined to be imbalanced, wherein when said ROM device is programmed in a software environment with said scrambled addresses, said distribution of binary 0's and binary 1's becomes more balanced.
A system for optimizing performance in a read-only memory (ROM) device wherein each memory location is addressable by a row address and a column address, said ROM device operating to contain a data map, comprising:
- means for analyzing said data map's distribution of binary 0's and binary 1's in a select portion of said ROM device to determine if said distribution is imbalanced in a normal addressing scheme;
- and
- means for scrambling said row address and said column address for memory locations in said select portion to generate scrambled addresses if said distribution is determined to be imbalanced, wherein when said ROM device is programmed in a software environment with said scrambled addresses, said distribution of binary 0's and binary 1's becomes more balanced.
Dependencies are inferred from the claim text.