Capacitor bias recovery methodology

A preamplifier circuit, comprising:

• a reference voltage circuit operable to generate a reference voltage at a reference node;
• a noise reduction capacitor coupled across the reference voltage circuit;
• a current bias boost recovery circuit operatively coupled to the reference node, and operable to increase a rate of charging of the noise reduction capacitor;
• a differential amplifier circuit having a first input coupled to the reference node and a second input coupled to a node associated with a bias current, and differential amplifier further having an output coupled to a bias capacitor, and wherein the differential amplifier charges or discharges the bias capacitor based on a differential voltage across the first and second inputs, thereby generating a bias voltage across the bias capacitor;
• a boost circuit coupled in a parallel with the differential amplifier circuit and operable to increase a rate of charging or discharging of the bias capacitor if a difference between the fist and second inputs exceeds a predetermined threshold;
• and
• a transconductance circuit coupled to the bias capacitor and operable to generate a bias current having a magnitude which is a function of the bias voltage.

A method of performing a head switch and a bias current switch in a single write step to a serial port register, comprising the steps of:

• transmitting a multi-bit code to the serial port register associated with a preamplifier circuit, wherein the multi-bit code comprises a first portion which indicates a desired head and a second portion which indicates a desired bias current for the desired head;
• asserting a head switch signal and a bias switch signal at about the same time in response to the multi-bit code transmission, wherein the assertion of the head switch signal and the bias switch signal cause the head switch and the bias current switch to proceed concurrently;
• and
• activating a current bias boost recovery circuit and a head select boost recovery circuit at about the same time in response to the head switch signal and the bias switch signal, respectively, wherein a recovery associated with a noise reduction capacitor and a bias capacitor is accomplished concurrently.