Method and apparatus for error correction of stored data
AssigneeInternational Business Machines Corporation
InventorsTeruhiko Ushio, Toshio Kanai
Life of this patent
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Abstract
Method and apparatus to correct an error of read-out data from a data storage medium, particularly a bit shift error, is described. The correction apparatus includes a gray bit detection circuit which flags bits with a phase shift exceeding a threshold and determines whether the previous or next bit cell has a smaller phase error. An RLL error detection circuit and a table containing valid bit combinations may be used in combination with the gray bit detector to correct errors on-the-fly without degrading performance. An advantage of the invention is that it allows correction of errors without regard to conventional ECC and its maximum number of errors.
Claims11
A method for correcting errors in a signal read from a data storage medium, comprising the steps of:
- converting the signal read from the medium into a first bit string;
- determining a phase shift for transitions in the signal;
- generating gray flag information indicating each phase shift exceeding a threshold;
- and
- if the first bit string is not a valid bit combination, then forming a second string by correcting error bits in the first bit string using the gray flag information and decoding the second bit string to obtain data;
- wherein the step of converting the signal further comprises the unordered steps of:
- detecting a frequency of the signal;
- dividing the signal into bit cells based on the frequency of the signal;
- detecting intersections of the signal and a slice signal level;
- and
- setting each bit cell not having an intersection to bit “0”.
A data storage device which corrects an error in data read from a data storage medium, comprising:
- a read channel which converts a signal read from the medium into a data bit string;
- a gray bit detection circuit which detects gray bits in the signal based on a phase shift of transitions in the signal and generates gray flag information according to the phase shift;
- and
- a decoder comprising;
- a run-length limited (RLL) error correction circuit which generates an RLL flag according to violations of selected run length rules;
- and a gray bit error correction circuit which corrects an error bit in the data bit string based on the gray flag information and the RLL flag.
A method for correcting errors in a signal read from a data storage medium, comprising the steps of:
- converting the signal read from the medium into a first bit string;
- determining a phase shift for transitions in the signal;
- generating gray flag information indicating each phase shift exceeding a threshold;
- and
- if the first bit string is not a valid bit combination, then forming a second bit string by correcting at least one error bit in the first bit string and decoding the second bit string to obtain data, the step of correcting the at least one error bit further comprising the non-ordered steps of:
- generating run-length limited (RLL) flag information indicating violations of a run-length limitation;
- checking a run-length of the first bit string;
- detecting the at least one error bit in the first bit string based on the run-length limitation;
- and
- correcting the at least one error bit using both the gray flag information and the RLL flag information.
A storage device comprising:
- means for detecting a frequency of a signal read from a medium;
- means for determining bit cells based on the frequency of the signal;
- a detector for detecting intersections of the signal and a slice signal level;
- means for setting each bit cell having an intersection to bit “1” and otherwise setting each bit cell not having an intersection to bit “0”;
- a gray bit detection circuit which sets a gray flag in a respective bit cell having a phase error (distance) between the intersection of the respective bit cell and a center of the respective bit cell greater than a selected threshold, in which case the gray bit detection circuit compares a first phase error (distance) between the intersection of the respective bit cell and the center of a next bit cell after the respective bit cell and a second phase error (distance) between the intersection of the respective bit cell and the center of a previous bit cell before the respective bit cell, and sets the gray flag in the previous bit cell or the next bit cell depending on which of the first and second phase errors (distances) is smaller;
- and
- a circuit for correcting an error in the respective bit cell based on the gray flag.
Dependencies are inferred from the claim text.