Circuits and methods for sampling an input signal in a charge redistribution digital to analog converter

A method of performing an analog to digital conversion in a charge redistribution circuit including a capacitor array of weighted capacitors and a transistor track switch for sampling an input signal onto the capacitor array comprising the steps of:

• stepping a common mode voltage by a step to a voltage sufficient to turn-on the transistor track switch during a sampling phase;
• during the sampling phase, performing the steps of:
• coupling a top plate of each of the capacitors to the common mode voltage through the track switch;
• and
• coupling a bottom plate of each of the capacitors to an input to sample an input signal;
• and
• during a conversion phase, performing the steps:
• decoupling the top plate of each of the capacitors from the common mode voltage;
• coupling the bottom plate of a selected one of the weighted capacitors to a first reference voltage, a weight of the selected one of the weighted capacitor proportional to the step in the common mode voltage;
• coupling the bottom plates of the remaining weighted capacitors to a second reference voltage;
• comparing the top plate voltage of the weighted capacitors against a comparison voltage proportional to the step in the common mode voltage;
• and
• if the top plate voltage is above the comparison voltage, coupling the selected capacitor to the second reference voltage.

An analog to digital converter comprising:

• an array of N number of binary-weighted capacitors, a selected capacitor M having a weight relative to a total capacitance of the array of ½M, each capacitor having a top plate and a bottom plate;
• a comparator having a first input coupled to said top plates of said capacitors and a second input coupled to a comparison voltage of ½MVDD, where VDD is a supply voltage;
• a transistor for selectively coupling the top plates of the capacitors to a common mode voltage VCM of approximately (1-½M)VDD, during a input sampling phase;
• and
• a successive approximation return path coupled to an output of the comparator and operable to:
• couple said bottom plates of the capacitors to an input during the sampling phase to sample an input signal having a voltage swing between approximately zero volts and VDD;
• couple said bottom plate of capacitor M to a high reference voltage VREF approximating VDD and the bottom plates of remaining capacitors of the array to a low reference voltage during a first period of a conversion phase;
• and
• if the top plate voltage is above the reference voltage of ½MVDD, couple capacitor M and capacitor M+1 to the low reference voltage during the second period of the conversion phase.