Flexible interface circuit and method for delta sigma A/D converters

A delta sigma analog-to-digital converter circuit comprising:

• (a) a delta sigma modulator receiving an analog input signal and a clock input signal for producing a 1-bit output signal representative of the analog input signal;
• and
• (b) a multi-mode interface circuit including
• i. a decoder for decoding a plurality of mode selection inputs to produce a plurality of control signals,
• ii. an oscillator circuit receiving a first control signal from the decoder for producing a first internal clock signal in response to the first control signal,
• iii. a first multiplexer having a first input coupled to do an external clock signal and a second input coupled to receive the first internal clock signal and a selection input coupled to receive a second control signal from the decoder for selectively switching the first internal clock signal or the external clock signal to a first conductor to produce a second internal clock signal thereon,
• iv. a code generator circuit receiving the second internal clock signal and the 1-bit data signal for producing the clock input signal, a third internal clock signal, and a fourth internal clock signal in response to the second internal clock signal, and for producing a phase-shift-modulated signal in response to both the second internal clock signal and the 1-bit data signal,
• v. a second multiplexer having a first port coupled to receive the third internal clock signal, a second port coupled to receive the fourth internal clock signal, a third port coupled to a predetermined signal, and a selection input coupled to receive a third control signal from the decoder for selectively switching one of the third and fourth clock signals onto a clock conductor to produce an output clock signal thereon;
• and
• vi. a third multiplexer having a first input coupled to receive the phase-shift-modulated signal, a second input coupled to receive the 1-bit data signal, and a selection input coupled to receive a fourth control signal from a decoder for selectively switching the phase-shift-modulated signal or the 1-bit data signal onto a data output conductor to produce a data output signal thereon.

A method of coupling a delta sigma modulator to a processor or digital filter, comprising:

• (a) decoding a plurality of mode selection inputs to produce a plurality of control signals;
• (b) enabling an oscillator to produce a first clock signal in response to a first control signal;
• (c) multiplexing the first clock signal or an external clock signal in response to a second control signal to produce a second clock signal;
• (d) producing a clock input signal in response to the second clock signal and applying the second clock signal as an input to the delta sigma modulator causing it to produce a 1-bit data signal, and dividing the second clock signal to produce third and fourth clock signals;
• (e) phase-modulating the clock input signal in accordance with the 1-bit data signal to produce a phase-shift-modulated signal;
• and
• (f) multiplexing one of the third and fourth clock signals, and a predetermined signal to a clock conductor in response to a third control signal, and multiplexing one of the phase-shift-modulated signal and the 1-bit data signal to a data output conductor in response to a fourth control signal.

An interface circuit for coupling a delta sigma modulator to a processor, comprising:

• (a) decoding means for decoding a plurality of mode selection inputs to produce a plurality of control signals;
• (b) means for enabling an oscillator to produce a first clock signal in response to a first control signal;
• (c) first multiplexing means for multiplexing one of the first clock signal and an external clock signal in response to a second control signal to produce a second clock signal;
• (d) means for applying the second clock signal as a clock input signal to the delta sigma modulator causing it to produce a 1-bit data signal;
• (e) dividing means for dividing the second clock signal to produce third and fourth clock signals;
• (f) phase-modulating means for phase-modulating the clock input signal in accordance with the 1-bit data signal to produce a phase-shift-modulated signal;
• (g) second multiplexing means for multiplexing one of the third and fourth clock signals and a predetermined signal to a clock conductor in response to a third control signal;
• and
• (h) third multiplexing means for multiplexing one of the phase-shift-modulated signal and the 1-bit data signal to a data output conductor in response to a fourth control signal.

A method of coupling a delta sigma modulator to a processor or digital filter, comprising:

• (a) decoding a plurality of mode selection inputs to produce a plurality of control signals;
• (b) enabling an oscillator to produce a first clock signal in response to a first control signal;
• (c) multiplexing the first clock signal or an external clock signal in response to a second control signal to produce a second clock signal;
• (d) producing a clock input signal in response to the second clock signal and applying the second clock signal as an input to the delta sigma modulator causing it to produce a 1-bit data signal, and dividing the second clock signal to produce third and fourth clock signals;
• (e) modulating the clock input signal in accordance with the 1-bit data signal to produce a modulated signal;
• (f) selectively (1) multiplexing one of the third and fourth clock signals, and a predetermined signal to a clock conductor in response to a third control signal or (2) applying the external clock signal to the clock conductor and multiplexing the external clock signal from the clock conductor to a multiplexer used in performing step (c) in response to a fourth control signal;
• and
• (g) multiplexing one of the modulated signal and the 1-bit data signal to a data output conductor in response to a fourth control signal.