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US 6,587,005 B2Granted
PLL circuit having a variable output frequency
AssigneeNEC Corporation
InventorMasaki Ichihara
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AssigneeNEC Corporation
InventorMasaki Ichihara
Estimating the term…
A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) having a parallel resonant circuit including a first capacitance implemented by a reverse-biased diode and a second capacitance implemented by MOS capacitors. Upon lock-in of the oscillation frequency with respect to the reference frequency, whether the oscillation frequency has a deviation is examined based on the tune voltage controlling the first variable capacitance. If a deviation is observed due to a temperature fluctuation etc., the control voltage for the second variable capacitance is corrected for compensating the deviation.
A phase locked loop (PLL) circuit comprising:
A method for controlling a phase locked loop (PLL) circuit including a voltage controlled oscillator (VCO), said VCO oscillating at an oscillation frequency based on first and second variable capacitances, said method comprising the steps of:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
For assuring initial synchronisation or for broadening the capture range: using an additional signal from outside the loop for setting or…
Details of the phase-locked loop: concerning mainly the controlled oscillator of the loop
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop:…
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using a lock detector
Term ended 21 Dec 2021 (estimated)
(a) Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit having a variable output frequency and, more particularly, to an improvement of such a PLL circuit to have an adjustable output frequency.
(b) Description of the Related Art
FIG. 1 is a block diagram of a conventional PLL circuit.
FIG. 2 is a circuit diagram of the VCO described in a publication.
FIG. 3 is a simplified equivalent circuit diagram of the VCO of FIG. 2.
Referring to FIG. 6, a PLL circuit, generally designated by numeral 10, according to a first embodiment of the present invention includes a VCO 11, an N-divider 17 for dividing the output signal from the VCO 41 by a number of N, a reference frequency oscillator 16, an R-divider 15 for dividing the reference frequency by a number of R, a register 18 for storing the number N, a register 19 for storing the number R, a phase comparator 14 for comparing the phase of the N-divided frequency signal output from the N-divider 18 against the phase of the R-divided frequency signal output from the R-divider 19, a charge pump 13 for receiving the output from the phase comparator 14, a loop filter 12 for passing the low-frequency component of the output from the charge pump 13 to generate a tune signal for the VCO 11, and a frequency control unit 20 for detecting the deviation of the output oscillation frequency of the VCO 11 from a specified frequency to control the oscillation frequency based on the detected deviation.
The tune signal from the low-pass filter 12 is substantially an integrated signal of the difference between the phase of the output from the N-divider 17 and the phase of the output from the R-divider 15. The output frequency from the VCO 11 is used as a is local oscillation signal during modulation or demodulation in a mobile telephone, for example.
The number N for dividing the output frequency from the VCO 11 in the N-divider 17 is stored in the register 18, which receives the number N from a CPU disposed outside the PLL circuit 10. The number R for dividing the reference frequency is stored in the register 19, which receives the number R from the CPU. The data of numbers N and R are fed to the PLL circuit 10 at the timing of the strobe signal.