Dynamic flip flop
AssigneeSeiko Instruments Inc.
InventorYoshihiro Shibuya
Life of this patent
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Abstract
It is intended to provide a dynamic flip flop that prevents a floating signal from maintaining a voltage below a substrate voltage level in a P-type semiconductor substrate and that prevents a floating signal from maintaining a voltage exceeding the substrate voltage level in an N-type semiconductor substrate. In the dynamic flip flop, an N-type MOSFET (5) controlled by an output signal MX from an inverter (2) and an N-type MOSFET (6) controlled by an output signal Q from an inverter (4) are provided as switches for short-circuiting a signal M and a signal QX to be brought into a floating state to a substrate.
Claims29
In a dynamic flip flop having first and second transmission gates formed in a substrate, the combination comprising:
- first and second switches controlled by clocks used for driving the transmission gates and being respectively connected to outputs of the first and second transmission gates for short-circuiting the outputs of the first and second transmission gates to a substrate voltage level whenever the respective transmission gates are placed in a non-conductive state, to thereby prevent the outputs of the transmission gates from one of falling below the substrate voltage level or exceeding the substrate voltage level due to a parasitic capacitance.
A flip flop comprising:
- a first transmission gate for receiving an input signal, a first clock signal, and an inverted first clock signal and outputting a signal corresponding to the input signal in accordance with the first clock signal and the inverted first clock signal;
- a first inverter for inverting the output signal of the first transmission gate;
- a second transmission gate for receiving an output signal of the first inverter, a second clock signal, and an inverted second clock signal and outputting a signal corresponding to the input signal in accordance with the second clock signal and the inverted second clock signal;
- a second inverter for inverting the output signal of the second transmission gate;
- a first switch for short-circuiting an output of the first transmission gate to a substrate voltage level whenever the first transmission gate is in a non-conductive state;
- and a second switch for short-circuiting an output of the second transmission gate to the substrate voltage level whenever the second transmission gate is in a non-conductive state.
An inverting circuit having one or more stages each comprising:
- an input terminal for supplying an input signal;
- an inverter connected to the input terminal for inverting the input signal and outputting an inverted signal in accordance with a clock signal;
- and a switch for short-circuiting the inverter input to a substrate voltage level in accordance with the clock signal to prevent the input of the inverter from one of falling below the substrate voltage level or exceeding the substrate voltage level due to a parasitic capacitance.
Dependencies are inferred from the claim text.