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US 6,586,978 B2Granted
Delay locked loop
AssigneeInfineon Technologies AG
InventorReidar Stief
Life of this patent
Estimating the term…
Abstract
A delay locked loop has a filter in order to set the delay time of a delay path in a manner dependent on the phase difference of input and output clock signals. The phase difference is ascertained by a phase detector. An additional control circuit determines the number of drive pulses of the filter and additionally controls the number of effective counter stages of a counter that forms the filter. The transient recovery time of the delay locked loop is thereby reduced.
Claims9
A delay locked loop, comprising:
- an input for obtaining a signal to be delayed;
- an output for providing a delayed signal;
- a delay circuit connected between said input and said output, said delay circuit having an output and a controllable delay time;
- a phase detector having an input coupled to said input for obtaining the signal to be delayed, said phase detector having another input coupled to said output of said delay circuit, said phase detector having an output;
- a filter having:
- a first input being controlled by said output of said phase detector,
- an output coupled to said delay circuit to control the delay time of said delay circuit,
- a multistage counter having counter stages connected between said first input and said output, and
- a second input;
- and
- a control logic circuit for feeding back said output of said filter to said second input of said filter in order to control a number of said counter stages that are effective between said first input of said filter and said output of said filter.
8 more elements
Dependencies are inferred from the claim text.