US 6,586,973 B2 · Output buffer circuit

Abstract

An output buffer circuit is provided for maintaining the slew rate of output waveforms of the output signal within a predetermined range regardless of changes of load on the output terminal. Series-connected feedback delay circuits (11-14) delay an input signal (IN) on the basis of the potential of an output signal (OUT) obtained through a feedback path (L1). Delay time of each feedback delay circuit varies according to load on an output terminal (2). Delay signals from the feedback delay circuits (11-14) are applied to one inputs of high-output selecting NAND gates (G11-G14), respectively. The NAND gates (G11-G14) also receive the input signal (IN) at their other inputs and output signals to gates of high output transistors (QP1-QP4), respectively. At the rise of the input signal (IN), the high output transistors (QP1-QP4) output the output signal (OUT) in response to the delay signals from the feedback delay circuits (11-14).

Claims11

Dependent claims

An output buffer circuit comprising:

an input terminal receiving an input signal;
an output terminal outputting an output signal;
at least one feedback delay circuit for receiving said input signal and said output signal as a feedback signal and for delaying said input signal by a plurality of delay times to output a plurality of delay signals, said plurality of delay times each varying according to a potential of said output signal;
and
at least one output buffer portion for outputting said output signal in response to said plurality of delay signals, a driving capability of said output buffer portion to said plurality of delay signals varying according to said plurality of delay times, wherein
said at least one output buffer portion includes a plurality of output buffer portions which are provided in a one-to-one correspondence with said plurality of delay signals.

3 more elements

An output buffer circuit comprising:

an input terminal receiving an input signal;
an output terminal outputting an output signal;
at least ones feedback delay circuit for receiving said input signal and said output signal as a feedback signal and for delaying said input signal by a delay time to output a delay signal, said delay time varying according to a potential of said output signal;
a plurality of data storage portions each for storing control data, receiving said delay signal at a different input time that elapses from a logic level transition on said input signal, and if said delay signal causes said logic level transition, setting said control data to indicate a halt in the operation;
and
at least one output buffer portion for outputting said output signal in response to said input signal,
wherein said at least one output buffer portion includes a plurality of output buffer portions provided in a one-to-one correspondence with said plurality of data storage portions, the operating/halting status of each of said plurality of output buffer portions being determined on the basis of said control data stored in a corresponding data storage portion.

4 more elements

Dependencies are inferred from the claim text.

Output buffer circuit

Life of this patent

Output buffer circuit

Life of this patent

Abstract

Claims11