Data latch with low-power bypass mode
AssigneeAltera Corporation
InventorsGregory Starr, Martin Langhammer, Chiao Kai Hwang
Life of this patent
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Abstract
A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.
Claims53
A latch circuit comprising:
- a flip-flop circuit including:
- a data input,
- a data output, and
- a clock input;
- and
- a multiplexer including:
- a first input connected to said data input,
- a second input connected to said data output,
- a latch output, and
- a control input for selecting one of said first-and second inputs as said latch output;
- wherein:
- said flip-flop circuit further comprises a low-power selection input connected to said control input of said multiplexer;
- and
- when said control input selects said first input as said latch output, said low-power selection input causes said flip-flop circuit to enter a low-power mode.
A latch circuit comprising:
- data latching means including a data input and a latched data output;
- means for bypassing said data latching means, said means for bypassing having an output selectable between said data input and said latched data output;
- wherein:
- said data latching means switches, responsive to said means for bypassing, between (a) operation in a normal mode, and (b) operation in a low-power mode.
Dependencies are inferred from the claim text.