Method and circuit for testing DC parameters of circuit input and output nodes

A method for testing drive current flowing through a circuit node of a circuit under test, the circuit under test including drive circuitry for driving the circuit node to a maximum and to a minimum voltage during testing, and a logic circuit for sampling the logic level of the circuit node, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the method comprising the steps of:

• determining a time interval for a signal transition on said circuit node that is less than an expected transition time of said signal transition and proportional to values of the capacitance of said circuit node, the input switching point voltage for said circuit node, and the current flowing through said circuit node;
• generating a signal transition on the circuit node via the drive circuitry in response to a first edge of a first clock which immediately follows an edge of a test clock used to generate test control signals, said first clock having a significantly higher frequency than said test clock;
• sampling a logic value of a voltage of the circuit node via the logic circuit in response to a subsequent edge of said first clock spaced from said first edge by said time interval;
• and
• passing or failing the test based on the sampled logic value of the voltage of the circuit node.

A control signal modifying circuit for modifying a test control signal generated by a test controller for controlling drive circuitry that drives a circuit node of a circuit under test and logic circuitry that samples the voltage of the circuit node, the test controller having a test clock for generating the test control signal and transitions between states for the test controller, the control signal modifying circuit comprising:

• receiving means for receiving the test control signal generated by the test controller;
• modifying means for modifying the test control signal to provide a predetermined time interval which is less than an expected signal transition time and proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node;
• and
• outputting means for outputting the modified test control signal to the drive circuitry and logic circuitry.

A control signal modifying circuit for modifying a test control signal generated by a test controller for controlling drive circuitry that drives a circuit node of a circuit under test and logic circuitry that samples the voltage of the circuit node, the test controller having a first test clock for generating the test control signal and transitions between states for the test controller, the control signal modifying circuit comprising:

• first receiving means for receiving the first test clock;
• second receiving means for receiving a second clock with a significantly higher frequency than the first test clock;
• detecting means for detecting an edge of the second test clock, which immediately follows an edge of the first test clock, and generates a signal transition on the circuit node via the drive circuitry;
• controlling means for controlling a subsequent edge of the second test clock to sample the voltage of the circuit node, such that a time interval between the edges of the second test clock is less than an expected transition time of the signal transition and proportional to values of the capacitance of the circuit node, the input switching point voltage for the circuit node, and the current flowing through the circuit node.

Testing circuitry for testing current flowing through a circuit node of a circuit under test, the circuit node having a capacitance, the testing circuitry comprising:

• drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing;
• a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the logic circuit having an input switching point voltage;
• a test controller for controlling the drive circuitry and the logic circuitry, the test controller having a test clock for generating the test control signal and transitions between states for the test controller;
• and
• a control signal modifying circuit for modifying the test control signal to provide a predetermined time interval which is less than an expected signal transition time and proportional to values of the capacitance of the circuit node, the input switching point voltage of the logic circuit, and the current flowing through the circuit node.

Testing circuitry for testing current flowing through a circuit node of a circuit under test, then circuit node having a capacitance, the testing circuitry comprising:

• drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing;
• a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the logic circuit having an input switching point voltage;
• a test controller for controlling the drive circuitry and the logic circuitry, the test controller having a first test clock for generating the test control signal and transitions between states for the test controller;
• a control signal modifying circuit having:
• first receiving means for receiving the first test clock;
• second receiving means for receiving a second clock with a significantly higher frequency than the first test clock;
• detecting means for detecting an edge of the second test clock, which immediately follows an edge of the first test clock, and generates a signal transition on the circuit node via the drive circuitry;
• controlling means for controlling a subsequent edge of the second test clock to sample the voltage of the circuit node, such that a time interval between the edges of the second test clock is less than an expected transition time of the signal transition and proportional to values of the capacitance of the circuit node, the input switching point voltage for the circuit node, and the current flowing through the circuit node.

A circuit for use in testing an enable input of a 3-state driver which drives a circuit node of an integrated circuit to a maximum and to a minimum voltage during testing, the driver having a data input, an enable input, and an output, said integrated circuit having an IEEE 1149.1 compliant test access port (TAP) and a TAP controller, and a logic circuit for sampling the logic level of the circuit node, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the circuit comprising:

• means for causing a signal transition at the circuit node via the drive circuitry and for disabling said driver during an Update-IR state of said TAP controller and for changing the logic value of said data input after said driver has been disabled and before sampling the logic value of said circuit node;
• and
• means for sampling a logic value of a voltage of the circuit node via the logic circuit under control of said clock signal at a predetermined time interval after the beginning of said signal transition, said time interval being less than the time for a maximum acceptable leakage current to discharge the voltage of said circuit node sufficiently to change the logic value of said circuit node, and the current flowing through the circuit node, said sampling means capturing the output logic value of said driver during a Capture-DR state of said TAP controller.

A method for testing leakage current flowing through a circuit node of a circuit under test, the circuit under test including drive circuitry that drives the circuit node to a maximum and to a minimum voltage during testing, and including a logic circuit that samples the logic level of the circuit node synchronously to a clock signal, the circuit node having a capacitance, and the logic circuit having an input switching point voltage, the method comprising the steps of:

• (a) determining a time interval for a signal transition on said circuit node that is less than an expected transition time of said signal transition and proportional to values of the capacitance of said circuit node, the input switching point voltage for said circuit node, and leakage current flowing through said circuit node;
• (b) driving the circuit node to a known voltage via the drive circuitry that drives the circuit node;
• (c) causing a signal transition at the circuit node via the drive circuitry;
• (d) sampling a logic value of a voltage of the circuit node via the logic circuit at a said time interval after the beginning of the signal transition;
• and
• (e) passing or failing the test based on the logic value sampled by the logic circuit during the signal transition.