Frequency sensing NMOS voltage regulator
AssigneeMicron Technology, Inc.
InventorsKent M. Kalpakjian, John D. Porter
Life of this patent
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Abstract
A frequency sensing NMOS voltage regulator is disclosed. A NMOS source follower transistor has a gate connected to a predetermined gate voltage, a drain coupled to an external supply voltage through a PMOS switching transistor, and a source connected to a load. The gate of the PMOS transistor is controlled by a delay circuit through which a pulse derived from the system clock is passed. Through the use of the delay circuit and the PMOS transistor, the amount of current produced by the NMOS transistor is made a function of the cycle rate of the system clock and the current provided by the NMOS transistor tracks the frequency-dependent current requirements of the load, resulting in a reduced variance of the supply voltage Vcc over a wide current range.
Claims11
A voltage regulator for a memory device comprising:
- means for generating a clock pulse signal based on a system clock signal;
- means for delaying said clock pulse signal;
- means for determining a control signal based on said clock pulse signal and a delay time of said delaying means;
- and
- means for turning on and off a supply voltage in response to said control signal to regulate said voltage.
A voltage supply circuit comprising:
- a control circuit adapted to output a first gate control voltage;
- a delay circuit adapted to receive a periodic pulse signal and controllably output a second gate control voltage;
- a first transistor having a first gate operatively connected to said control circuit and adapted to receive said first gate control voltage;
- a second transistor having a second gate operatively connected to said delay circuit and adapted to receive said second gate control voltage, said first and second transistors operatively connected in series between a source of constant potential voltage and an electrical load, wherein said delay circuit exhibits a characteristic signal delay and wherein said delay circuit is adapted to output said second gate voltage when said characteristic signal delay has a duration shorter than a pulse length of said periodic pulse signal.
A method of regulating an electrical voltage applied to an electrical load comprising:
- comparing a duration of a clock pulse to a time delay of a delay circuit;
- and
- turning off a transistor operatively connected between a source of electrical supply and an electrical load during a time when said duration has exceeded said time delay, whereby said electrical voltage is regulated across said electrical load.
A voltage control signal adapted to control a voltage regulator circuit, said signal comprising:
- a first state and a second state, said signal exhibiting said first state during a first time when a duration of a clock pulse has not exceeded a delay duration of a delay circuit, said signal exhibiting said second state during a second time when a duration of said clock pulse has exceeded said delay duration of said delay circuit, said signal adapted to control a transistor operatively connected between a voltage supply and a load, whereby a voltage across said load is regulated.
Dependencies are inferred from the claim text.