Dual damascene integration scheme for preventing copper contamination of dielectric layer

A semiconductor device, comprising:

• a first metallization layer;
• a first diffusion barrier layer disposed over said first metallization layer;
• a second etch stop layer disposed over and spaced from said first diffusion barrier layer;
• a third etch stop layer formed from silicon oxide between said first diffusion barrier layer and said second etch stop layer;
• a first dielectric layer disposed over said second etch stop layer;
• a first etch stop layer disposed over said first dielectric layer;
• a second dielectric layer disposed over said first etch stop layer;
• a trench extending through said second dielectric layer and said first etch stop layer;
• and
• a via extending from said trench through said first dielectric layer, said second etch stop layer, and said first diffusion barrier layer to said first metallization layer, wherein said third etch stop layer has a thickness of at least 50 angstroms to about 120 angstroms.

A semiconductor device, comprising:

• a first metallization layer;
• a first diffusion barrier layer disposed over said first metallization layer;
• a second etch stop layer disposed over and spaced from said first diffusion barrier layer;
• a first dielectric layer disposed over said second etch stop layer;
• a first etch stop layer disposed over said first dielectric layer;
• a second dielectric layer disposed over said first etch stop layer;
• a trench extending through said second dielectric layer and said first etch stop layer;
• a via extending from said trench through said first dielectric layer, said second etch stop layer, and said first diffusion barrier layer to said first metallization layer;
• and
• a sidewall diffusion barrier layer disposed on sidewalls of said via and said trench wherein said sidewall diffusion barrier layer is formed from the same material as said first diffusion barrier layer.

A semiconductor device, comprising:

• a first metallization layer;
• a first dielectric layer disposed over said first metallization layer;
• a second dielectric layer disposed over said first dielectric layer, said second dielectric layer defining a trench extending through said second dielectric layer to said first dielectric layer and said first dielectric layer defining a via extending from said trench through said first dielectric layer to said first metallization layer;
• a first sidewall diffusion barrier layer formed from a first material disposed on sidewalls of said via and trench;
• a second sidewall diffusion barrier layer formed from a second material disposed over said first sidewall diffusion barrier layer, said second material different than said first material;
• and
• a conductive material disposed within said via and trench, wherein said first sidewall diffusion barrier includes silicon nitride, wherein said first sidewall diffusion barrier layer is formed by reverse sputtering.