Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines

A packaged power transistor, comprising:

• an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;
• a ceramic substrate mounted within the slot;
• a gate electrode strip line that is patterned on said ceramic substrate and extends opposite a bottom of the slot, said gate electrode strip line having an upper surface that is coplanar with the primary surface of said electrically conductive flange;
• and
• a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to a first end of said gate electrode strip line and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface.

A packaged power transistor device, comprising:

• an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;
• an integrated circuit substrate mounted to a bottom of the slot, said integrated circuit substrate comprising a semiconductor layer that is electrically coupled to said flange, a dielectric layer on the semiconductor layer and a gate interconnect on the dielectric layer, said gate interconnect comprising a gate electrode strip line having an upper surface that is coplanar with the primary surface of said electrically conductive flange;
• and
• a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to the gate interconnect and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface.

A packaged power transistor device, comprising:

• an electrically conductive flange having a slot therein that is recessed relative to a primary surface of said electrically conductive flange;
• an integrated circuit substrate mounted to a bottom of the slot, said integrated circuit substrate comprising a semiconductor layer that is electrically coupled to said flange, a dielectric layer on the semiconductor layer and a gate interconnect on the dielectric layer, said gate interconnect comprising a gate electrode strip line or a gate metal strap;
• and
• a vertical power MOSFET having a semiconductor region therein, a source electrode that extends adjacent a first surface of the semiconductor region and is electrically coupled and mounted to a first portion of said flange located outside the slot, a gate electrode that is electrically coupled and mounted to the gate interconnect and a drain electrode that extends adjacent a second surface of the semiconductor region, which is opposite the first surface;
• wherein said gate interconnect comprises a gate electrode strip line;
• wherein said gate electrode strip line comprises first and second strip line segments that are joined together by a capacitor electrode;
• wherein the capacitor electrode and the semiconductor layer collectively form opposing electrodes of a capacitor;
• and
• wherein an upper surface of said gate electrode strip line is coplanar with the primary surface of said electrically conductive flange.