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US 6,586,830 B2Granted
Semiconductor device with an interposer
AssigneeSony Corporation
InventorTakashi Saito
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AssigneeSony Corporation
InventorTakashi Saito
Estimating the term…
An improved semiconductor chip interconnection advantageously employs a thin conductive layer that is used to form conductive members located between two nonconductive layers. The upper nonconductive layer has openings formed therein through which electrical connections are made between contacts in the chip member and the conductive members. The conductive members preferably have portions which are substantially parallel to a bottom surface of the semiconductor chip located between nonconductive layers and an upper nonconductive layer has openings formed therein through which electrical connections are made with the semiconductor chip. The conductive members have portions that extend downward away from the bottom surface of the chip.
A semiconductor device comprising:
The semiconductor device as claimed in claim 3, wherein;
An interposer to be affixed and connected to a semiconductor chip as to form a semiconductor package comprising:
A semiconductor mounting structure comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Leaded components: characterised by the leads
Characterised by their insulating layers or insulating parts: shapes or dispositions thereof
Package configurations: characterised by the relative positions of pads or connectors relative to package parts
Shapes of wire connectors: the connected ends being ball-shaped
Term ended 17 May 2021 (estimated)
The present invention relates to a semiconductor device, an interposer thereof, and a method of manufacturing the same, and in particular, the present a invention relates to a semiconductor device having a CSP (Chip Size Package or Chip Scale Package) structure, an interposer thereof, and a method of manufacturing the same.
In order to cope with a demand for a compact design of recent electronic products, necessity of a high density packaging for electronic parts, in particular, for semiconductor devices is increasing. Therefore, a CSP (Chip Size Package) is adopted as one of such high density packages instead of a conventional plastic package.
An internal structure of the CSP can be divided roughly into two types depending on a method of interconnection between electrodes of an IC (Integrated Circuit) chip (which may be referred to also as a chip or a semiconductor chip hereinafter) and an interposer (wiring board). One of two types of the CSP is a wire bonding type CSP as indicated in FIG. 16, wherein after connecting an interposer 21A and electrodes of an IC chip 10 to each other with a copper wire 17, they are packaged with a resin 18 to form a semiconductor package 20, which is then connected to a mounting substrate via a solder bump 11.
In the accompanying drawings:
FIG. 1 is a schematic diagram illustrating a state of packaging of a CSP mounted on a mounting substrate according to one embodiment of the invention;
FIGS. 2A to 2B are diagrams illustrating a deformation of external terminals due to thermal stresses applied to the CSP, wherein FIG. 2A depicts a normal state while FIG. 2B depicts a deformed state thereof;
Referring now to the accompanying drawings, preferred embodiments of the invention will be described in the following.
In the semiconductor device, the interposer thereof, and the method of manufacturing the same according to the invention described above, an external electrode 6 preferably projects from a semiconductor package 7 for constituting a semiconductor chip size package as indicated in FIG. 1.
Further, the above-mentioned external terminal may be allowed to bend from its non-projecting state downwardly as shown, for example, in FIG. 15.