Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench;
• and
• a second MISFET formed on the substrate in a second active region whose periphery is defined by an element isolation trench;
• and
• wherein a first gate electrode of said first MISFET is formed on the substrate and extends over the first active region from one end of the first active region to another, opposite end thereof in a direction of gate width of said first MISFET,
• wherein a second gate electrode of said second MISFET is formed on the substrate and extends over the second active region from one end of the second active region to another, opposite end thereof in a direction of gate width of said second MISFET,
• wherein a gate length of the first gate electrode in a first boundary region defined between the first active region and the element isolation trench thereof is greater than a gate length thereof in a central portion of the first active region,
• wherein a gate length of the second gate electrode in a second boundary region defined between the second active region and the element isolation trench thereof is substantially equal to a gate length thereof in a central portion of the second active region, the gate-width direction and the gate-length direction of each of said first and second MISFETs correspond to the direction of channel width and the direction of channel length thereof, respectively, and
• wherein the first gate electrode in the first boundary region covers the entirety of a side of the first boundary region extending in the gate-length direction of the first MISFET.

A semiconductor integrated circuit device comprising:

• a memory cell comprised of a pair of drive MISFETs, a pair of load MISFETs and a pair of transfer MISFETs, each drive MISFET being formed on a substrate in a corresponding first active region whose periphery is defined by an element isolation trench, and each load MISFET being formed on the substrate in a corresponding second active region whose periphery is defined by an element isolation trench,
• wherein a gate electrode of said each drive MISFET is formed on the substrate and extends over the first active region thereof from one end of that first active region to another, opposite end thereof in a direction of gate width of that drive MISFET,
• wherein a gate length of the gate electrode of said each drive MISFET in a boundary region defined between the first active region and the element isolation trench thereof is greater than a gate length thereof in a central portion of the first active region,
• wherein a gate electrode of each load MISFET is formed on the substrate and extends over the second active region thereof, from one end of that second active region to another, opposite end thereof in a direction of gate width of that load MISFET, and
• wherein a gate length of the gate electrode of said each load MISFET in said second active region is greater than the gate length of the gate electrode of said each drive MISFET in a central portion of said first active region, the gate-width direction and the gate-length direction of said each drive MISFET and said each load MISFET correspond to the direction of channel width and the direction of channel length thereof, respectively.

A semiconductor integrated circuit device comprising:

• a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench;
• and
• a second MISFET formed on the substrate in a second active region whose periphery is defined by an element isolation trench;
• and
• wherein a first gate electrode of said first MISFET is formed on the substrate and extends over the first active region from one end of the first active region to another, opposing end thereof in a direction of gate width of said first MISFET,
• wherein a second gate electrode of said second MISFET is formed on the substrate and extends over the second active region from one end of the second active region to another, opposing end thereof in a direction of gate width of said second MISFET,
• wherein a gate length of the first gate electrode in a first boundary region defined between the first active region and the element isolation trench thereof is greater than a gate length thereof in a central portion of the first active region,
• wherein a gate length of the second gate electrode in a second boundary region defined between the second active region and the element isolation trench thereof is greater than a gate length thereof in a central portion of the second active region, the gate-width direction and the gate-length direction of each of said first and second MISFETs correspond to the direction of channel width and the direction of channel length thereof, respectively, and
• wherein the first gate electrode in the first boundary region covers the entirety of a side of the first boundary region extending in the gate-length direction of said first MISFET.

A semiconductor integrated circuit device comprising:

• a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench;
• and
• a second MISFET formed on the substrate in a second active region whose periphery is defined by an element isolation trench,
• wherein a first gate electrode of said first MISFET is formed on the substrate and extends over the first active region from one end of the first active region to another, opposite end thereof in a direction of gate width of said first MISFET,
• wherein a gate length of the first gate electrode in a first boundary region defined between the first active region and the element isolation trench thereof is greater than a gate length in a central portion of the first active region,
• wherein said first gate electrode in the first boundary region covers the entirety of one side of the first boundary region extending in the gate-length direction, and parts of two other sides thereof extending in the gate-width direction,
• wherein a second gate electrode of said second MISFET is formed on the substrate and extends over the second active region from one end of the second active region to another, opposite end thereof in a direction of gate width of said second MISFET,
• wherein a gate length of the second gate electrode in a second boundary region defined between the second active region and the element isolation trench is greater than a gate length in a central portion of the second active region, the gate-width direction and the gate-length direction of each of said first and second MISFETs correspond to the direction of channel width and the direction of channel length thereof, respectively,
• wherein said second gate electrode in the second boundary region covers (i) the entirety of one side of the second boundary region extending in the gate-length direction and (ii) parts of two other sides thereof extending in the gate-width direction, and
• wherein said first active region is formed in a first well region of a first conductivity type, said second active region is formed in a second well region of the first conductivity type, and said first well region and said second well region are formed to be electrically isolated from each other.