Back to results
US 6,586,793 B2Granted
Ferroelectric memory and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsKeitaro Imai, Koji Yamakawa
Life of this patent
Estimating the term…
Abstract
A ferroelectric memory includes first and second plugs respectively connected to one and the other of source/drain regions of the transistor formed on a semiconductor wafer. A first capacitor electrode is connected to the first plug and located at a position above the transistor. The first capacitor electrode includes first and second capacitor faces on the second plug side and a side reverse thereto, respectively. A ferroelectric film is disposed on the first capacitor face. A second capacitor electrode is connected to the second plug and located at a position above the transistor. The second capacitor electrode is disposed on the first capacitor face through the ferroelectric film.
Claims18
A ferroelectric memory comprising:
- a semiconductor substrate;
- first, second, and third source/drain regions formed in a surface of the substrate, the first source/drain region being interposed between the second and third source/drain regions;
- first and second gate electrodes facing, through a gate insulating film, a first channel region between the first and second source/drain regions, and a second channel region between the first and third source/drain regions, respectively;
- an inter-level insulating film covering the first, second, and third source/drain regions;
- first, second, and third plugs penetrating the inter-level insulating film, and electrically connected to the first, second, and third source/drain regions, respectively;
- a first capacitor electrode disposed above the first source/drain region, and electrically connected to the first source/drain region via the first plug;
- first and second capacitor insulating films each comprising a ferroelectric film, formed on side surfaces of the first capacitor electrode facing the second and third source/drain regions;
- second and third capacitor electrodes disposed above the second and third source/drain regions, and electrically connected to the second and third source/drain regions via the second and third plugs, respectively, the second and third capacitor electrodes facing the first capacitor electrode through the first and second capacitor insulating films, respectively;
- a fourth source/drain region formed in the surface of the substrate, the second source/drain region being interposed between the first and fourth source/drain regions;
- a third gate electrode facing through a gate insulating film a third channel region between the second and fourth source/drain regions;
- the inter-level insulating film covering the fourth source/drain region;
- a fourth plug penetrating the inter-level insulating film, and electrically connected to the fourth source/drain region;
- a fourth capacitor electrode disposed above the fourth source/drain region, and electrically connected to the fourth source/drain region via the fourth plug;
- and
- a third capacitor insulating film comprising a ferroelectric film, formed on a side surface of the fourth capacitor electrode facing the second source/drain region, the second capacitor electrode facing the fourth capacitor electrode through the third capacitor insulating film,
- wherein the first and third capacitor insulating films comprise respective standing portions of a U-shaped insulating film disposed between the first and fourth capacitor electrodes, and the second capacitor electrode is disposed inside the U-shaped insulating film, and is electrically connected to the second plug via an upper plug penetrating a bottom portion of the U-shaped insulating film.
13 more elements
A ferroelectric memory comprising:
- a semiconductor substrate;
- a plurality of source/drain regions formed in a surface of the substrate;
- a plurality of gate electrodes respectively facing, through gate insulating films, channel regions between the source/drain regions;
- an inter-level insulating film covering the source/drain regions;
- a plurality of connection plugs penetrating the inter-level insulating film, and electrically connected to the respective source/drain regions;
- a plurality of first capacitor electrodes and a plurality of second capacitor electrodes alternately disposed one by one above the source/drain regions, and having side surfaces facing each other, the first and second capacitor electrodes being electrically connected to the source/drain regions via the connection plugs;
- and
- a plurality of capacitor insulating films, each comprising a ferroelectric film, sandwiched between the side surfaces of the first and second capacitor electrodes;
- wherein, between each pair of adjacent two of the first capacitor electrodes, a pair of adjacent two of the capacitor insulating films comprise respective standing portions of a U-shaped insulating film disposed between the pair of first capacitor electrodes, and a corresponding one of the second capacitor electrodes is disposed inside the U-shaped insulating film, and is electrically connected to the connection plug via an upper plug penetrating a bottom portion of the U-shaped insulating film.
6 more elements
Dependencies are inferred from the claim text.