US 6,586,766 B2Granted

Semiconductor device with semiconductor circuit comprising semiconductor units, and method of fabricating it

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsShunpei Yamazaki, Etsuko Fujimoto, Atsuo Isobe, Toru Takayama, Kunihiko Fukuchi

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Abstract

The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.

Claims14

Dependent claims

A personal computer comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A personal computer comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

A video camera comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A video camera comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

A mobile computer comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A mobile computer comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

A goggle type display comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A goggle type display comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

A player incorporating a recording medium comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A player incorporating a recording medium comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

A digital camera comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A digital camera comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

A projector comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than the first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than the first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
wherein an edge portions of said side walls coincide with a boundary between said second impurity region and said second source region and between said third impurity region and said second drain region, and
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

15 more elements

A projector comprising:

a substrate;
a pixel matrix circuit comprising at least one first thin film transistor over said substrate, said first thin film transistor comprising:
a first source region;
a first drain region;
a first channel region between said first source region and said first drain region;
a first N-type impurity region having a lower concentration than said first source and drain regions, provided between said first source region and said first channel region;
a second N-type impurity region having a lower concentration than said first source and drain regions, provided between said first drain region and said first channel region;
a first gate electrode having a multi-layered structure over said first channel region with a first insulation film interposed therebetween;
an insulator formed on an upper surface and side surfaces of said gate electrode;
an interlayer insulation film formed on said insulator,
wherein an edge portions of said insulator coincide with a boundary between said first N-type impurity region and said first source region and between said second N-type impurity region and said first drain region, and
at least one driving circuit for driving said pixel matrix circuit comprising at least one second thin film transistor over said substrate, said second thin film transistors comprising:
a second source region;
a second drain region;
a second channel region between said second source region and said second drain region;
a second impurity region having a lower concentration than the second source and drain regions, provided between said second source region and said second channel region;
a third impurity region having a lower concentration than the second source and drain regions, provided between said second drain region and said second channel region;
a second gate electrode having a multi-layered structure over said second channel region with a second insulation film interposed therebetween;
side walls formed adjacent to side surfaces of said second gate electrode;
an interlayer insulation film formed on upper surface of said gate electrode,
wherein a width of said first and second N-type impurity regions are larger than that of said second and third impurity regions.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/124,373Filed 18 Apr 2002 · division
Priority: JP 10-20237616 Jul 1998
Published: US 2002/0149016 A117 Oct 2002
Granted: 1 Jul 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 86/60
Characterised by multiple TFTs: wherein the TFTs are in active matrices
H10D 86/431
Characterised by multiple TFTs: having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
H10D 86/451
Characterised by multiple TFTs: characterised by the compositions or shapes of the interlayer dielectrics
G02F 1/13454
Conductors connecting electrodes to cell terminals: drivers integrated on the active matrix substrate