Plastic chip-scale package having integrated passive components

A semiconductor device comprising a high performance integrated circuit chip having an outline assembled in a plastic package having an outline that is approximately the same as said outline of said chip, comprising:

• a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, said layers mutually adhering to form said substrate;
• said plurality of patterned insulating layers and said patterned electrically conductive layers comprising a plurality of passive electrical components and said patterned electrically conductive layers comprising routing lines, each of said lines terminating in a first plurality of bondable contact pads and a second plurality of solderable contact pads;
• said components and lines forming a web, configured mostly in a narrow peripheral band at least partially around a central substrate area, and operable with high performance in conjunction with said chip;
• said chip attached to said central substrate area and electrically connected to said first plurality of contact pads, respectively, whereby said passive components are integrated with said chip;
• and
• plastic encapsulation material surrounding said chip, said first plurality of contact pads, and said passive components such that the outline of said material is approximately the same as said outline of said chip.