Reducing copper line resistivity by smoothing trench and via sidewalls

A method of fabricating an integrated circuit, comprising the steps of:

• forming a interlevel dielectric layer over a semiconductor body;
• forming an intrametal dielectric layer over said interlevel dielectric layer;
• etching a trench in said intrametal dielectric layer and a via in said interlevel dielectric layer;
• depositing a thin liner over said intrametal dielectric layer including within said trench and said via, wherein said thin liner provides a smoother surface to said trench and via;
• directionally etching said thin liner in a horizontal direction to remove said thin liner from a bottom of said via;
• depositing a barrier layer over said thin liner;
• forming a copper interconnect structure in said trench and said via after the steps of depositing the thin liner and depositing the barrier layer.

A method of fabricating an integrated circuit, comprising the steps of:

• forming a dielectric layer over a semiconductor body;
• etching a hole in said dielectric layer, wherein sidewalls of said hole have a rough surface;
• depositing a thin liner over said dielectric including within said hole, wherein a surface of said thin liner within said hole has a smother surface than said rough surface and wherein said thin liner comprises silicon dioxide;
• depositing a barrier liner over said thin liner;
• forming a copper interconnect structure In said hole after the steps of depositing the thin liner and depositing the barrier layer.