Low sheet resistance of titanium salicide process

A method of Titanium salicide formation on the silicon substrate using a silicon injection process comprising steps of:

• providing a silicon substrate;
• creating a CMOS device structure on said substrate, said CMOS device comprising source/drain regions created in said substrate, said CMOS device further comprising a patterned and etched layer of polysilicon overlying said substrate, said patterned and etched layer of polysilicon forming a layer of gate electrode material of said CMOS device, said source/drain regions created in said substrate having been created as impurity implantations into said substrate being self-aligned with said patterned and etched layer of polysilicon;
• then
• vacuum baking said substrate;
• then
• performing Pre-Amorphorizing Implantation (PAT) upon said substrate;
• then
• performing a one step HF dip of said substrate;
• then
• (1) depositing a layer of titanium over the source/drain regions in said substrate and over the patterned and etched layer of polysilicon overlying said substrate;
• (2) performing a first Rapid Thermal Annealing process of said substrate;
• (3) performing a selective etching of said substrate thereby forming contact areas for the self-aligned source/drain regions in said substrate;
• and
• (4) performing a second Rapid Thermal Annealing process of said substrate, thereby forming a layer of low sheet resistance titanium silicide over said source/drain regions in said substrate.