US 6,586,305 B2Granted

Method for producing transistors in integrated semiconductor circuits

AssigneeInfineon Technologies AG

InventorWerner Graf

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Abstract

Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel area by changing the ionization energy (work function) of the electrons. Transistors in semiconductor circuits, which have both a memory area and a logic area, are produced either using different dopings for pMOS and NMOS transistors in the logic area (dual work function) or using common source/drain electrodes in the memory area (borderless contact), with all the transistors in the semiconductor circuit receiving the same gate doping in the latter case. A method is proposed by which a dual work function and a borderless contact can be produced at the same time. Furthermore, the method results without any additional effort in a trench between the gate layer stacks of the memory area and of the logic area, which prevents lateral ion diffusion.

Claims15

Dependent claims

A method for producing of an integrated semiconductor circuit, which comprises the steps of:

providing a semiconductor substrate having a first surface area and a second surface area being adjacent to the first surface area;
applying a first conductive layer to the semiconductor substrate;
producing a first covering layer on the first conductive layer, the first covering layer extending over the first surface area of the semiconductor substrate;
applying a second conductive layer over the first covering layer and the first conductive layer;
producing a second covering layer on the second conductive layer in the second surface area of the semiconductor substrate, the second covering layer being separated by a boundary area of a predetermined minimum width from a boundary between the first surface area and the second surface area;
and
carrying out an etching process to remove the second conductive layer selectively with respect to the first covering layer and with respect to the second covering layer, as a result of which the second conductive layer, and also the first conductive layer in the boundary area are removed, and a trench being formed between the first covering layer and the second covering layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/223,034Filed 16 Aug 2002
Priority: DE 101 40 04716 Aug 2001
Published: US 2003/0049906 A113 Mar 2003
Granted: 1 Jul 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10D 84/0177
Manufacturing their gate conductors: the gate conductors having different materials or different implants
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe