Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors

A method of forming a semiconductor-on-insulator transistor comprising the following steps:

• forming a semiconductor material layer on a substrate;
• patterning a transistor gate line opening within the semiconductor material layer, the transistor gate line opening having opposing sidewalls;
• forming a gate dielectric layer over the gate line opening sidewalls;
• after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;
• providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening;
• and
• forming a pair of source/drain regions of the semiconductor-on-insulator transistor within the semiconductor material layer in operable proximity to the channel region, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening, one of the source/drain diffusion regions comprising an outer region, and the other of the source/drain diffusion regions comprising an inner diffusion region;
• masking the semiconductor material layer to define a masked portion and an unmasked portion;
• and
• ion implanting into the unmasked portion of the semiconductor material layer to form an electrically conductive plug contact to the inner diffusion region through the semiconductor material layer.

A method of forming a semiconductor-on-insulator transistor comprising the following steps:

• forming a semiconductor material layer on a substrate;
• patterning a transistor gate line opening within the semiconductor material layer, the transistor gate line opening having opposing sidewalls;
• forming a gate dielectric layer over the gate line opening sidewalls;
• after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;
• providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening;
• and
• after the filling the transistor gate line, forming a pair of source/drain regions of the semiconductor-on-insulator transistor in operable proximity to the channel region, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening.

A method of forming a semiconductor-on-insulator transistor comprising the following steps:

• forming a semiconductor material layer on a substrate;
• patterning a transistor gate line opening completely through the semiconductor material layer, the transistor gate line opening having opposing sidewalls;
• forming a gate dielectric layer over the gate line opening sidewalls;
• after forming the gate dielectric layer, filling the transistor gate line opening with electrically conductive material;
• providing a channel region within the semiconductor material layer operably adjacent the transistor gate line opening;
• and
• forming a pair of source/drain regions of the semiconductor-on-insulator transistor in operable proximity to the channel region by ion implanting of a conductivity enhancing impurity using two different masking steps to two different elevations within a singly formed portion of the semiconductor material layer, the drain region being formed on one of the sidewalls of the transistor gate line opening and not extending to below the transistor gate, there being no drain region on the other of the opposing sidewall of the transistor gate line opening.