Mixed mode process
AssigneeUnited Microelectronics Corp.
InventorChing-Huei Tsai
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Abstract
A gate oxide layer, a first polysilicon layer, a polycide layer and a first interpolysilicon oxide (IPO) layer are sequentially formed on a semiconductor substrate. The first IPO layer, the polycide layer and the first polysilicon layer are then etched to form a gate and a bottom electrode plate. A second IPO layer and a polysilicon layer are then formed on the substrate and are etched to form a conductive wire and a top electrode plate thereafter. Finally, a spacer is formed, and an ion implantation process and a self-aligned suicide (salicide) process are performed to complete a mixed mode process for the formation of the conductive wire, a metal-oxide-semiconductor (MOS) transistor and a capacitor structure.
Claims22
A mixed mode process for integration circuits comprising:
- providing a semiconductor substrate, a surface of the semiconductor substrate comprising at least a conductive region, a metal-oxide-semiconductor (MOS) transistor region and a capacitor region;
- sequentially forming a gate oxide layer, a first conductive layer, a first silicide layer and a first oxide layer on the semiconductor substrate;
- performing a first photo-etching-process (PEP) to remove portions of the first oxide layer, first silicide layer and the first conductive layer to simultaneously form a first stacked structure and a second stacked structure respectively in the MOS transistor region and the capacitor region;
- sequentially forming a second oxide layer and a second conductive layer on the semiconductor substrate to cover the first and second stacked structures;
- performing a second PEP to remove portions of the second conductive layer to simultaneously form a conductive wire and a top electrode plate of a capacitor respectively in the conductive region and on the second stacked structure;
- forming a dielectric layer on the semiconductor substrate to cover the conductive wire, the first stacked structure, the top electrode plate and the second stacked structure;
- performing an etching process to remove portions of the dielectric layer and the second oxide layer to form a spacer on either sides of the conductive wire, the top electrode plate and the second stacked structure;
- and
- performing a self-aligned silicide (salicide) process to form a second silicide layer respectively on the conductive wire, the top electrode plate and portions of the surface of the semiconductor substrate adjacent to either sides of the first stacked structure in the MOS transistor region.
A mixed mode process for integration circuits comprising:
- providing a semiconductor substrate, a surface of the semiconductor substrate comprising at least a conductive region, a MOS transistor region and a capacitor region, either one of the conductive region and the capacitor region comprises a field oxide layer formed on the semiconductor substrate;
- sequentially forming a gate oxide layer, a first conductive layer and a first silicide layer on the semiconductor substrate;
- performing a first PEP to remove portions of the first silicide layer and the first conductive layer to simultaneously form a first stacked structure and a second stacked structure respectively in the MOS transistor region and the capacitor region;
- sequentially forming a first oxide layer and a second conductive layer on the semiconductor substrate to cover the first and second stacked structures;
- performing a second PEP to remove portions of the second conductive layer to simultaneously form a conductive wire and a top electrode plate of a capacitor respectively in the conductive region and on the second stacked structure;
- forming a dielectric layer on the semiconductor substrate to cover the conductive wire, the first stacked structure, the top electrode plate and the second stacked structure;
- performing an etching process to remove portions of the dielectric layer and the first oxide layer to form a spacer on either sides of the conductive wire, the top electrode plate and the second stacked structure;
- performing an ion implantation process to form a doped region in portions of the semiconductor substrate adjacent to either sides of the first stacked structure;
- and
- performing a salicide process to form a second silicide layer respectively on the conductive wire, the top electrode plate and portions of the surface of the semiconductor substrate adjacent to either sides of the first stacked structure in the MOS transistor region.
Dependencies are inferred from the claim text.