Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks

A method comprising:

• masking off a wafer containing CMOS circuits to expose NMOS transistors and cover PMOS transistors;
• performing a source drain extension implant on the NMOS transistors;
• performing a low threshold voltage first halo implantation on the NMOS transistors;
• masking off the wafer containing CMOS circuits to expose PMOS transistors and cover NMOS transistors;
• performing a source drain extension implant on the PMOS transistors;
• performing a high threshold voltage second halo implantation on the PMOS transistors;
• masking off the wafer containing CMOS circuits to expose high threshold voltage NMOS transistors and low threshold voltage PMOS transistors while covering low threshold voltage NMOS transistors and high threshold voltage PMOS transistors;
• and
• enhancing the threshold voltage of the high threshold voltage NMOS transistor while compensating the threshold of the low threshold voltage PMOS transistor with a single third implantation.