Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
AssigneeIntel Corporation
InventorsSteven Towle, Hajime Sakamoto, Dongdong Wang
Life of this patent
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AssigneeIntel Corporation
InventorsSteven Towle, Hajime Sakamoto, Dongdong Wang
Estimating the term…
A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
A method for use in fabricating a microelectronic device, comprising:
The method claimed in claimed 1 comprising:
A method for use in packaging a microelectronic device, comprising:
A method for use in packaging a microelectronic device comprising:
Dependencies are inferred from the claim text.