Method of performing timing-driven layout

A method of performing timing-driven layout of a circuit, comprising the steps of:

• (a) generating an initial layout result through placement of functional blocks of the circuit;
• (b) estimating wiring capacitance values or the respective blocks using the initial layout result;
• (c) calculating fan-out capacitance limitation values for the respective blocks using the wiring capacitance values of the blocks estimated in the step (b);
• each of the fan-out capacitance limitation values representing a maximum capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
• (d) comparing a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
• (e) defining the blocks whose wiring capacitance values do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result;
• and
• (f) changing circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.

A computer program product having a computer readable medium and a computer program recorded thereon, the computer program being operable to perform a method of performing timing-driven layout of a circuit, the product comprising:

• (a) code that generates an initial layout result through placement of functional blocks of the circuit and routing of wiring lines for the blocks;
• (b) code that calculates wiring capacitance values of the respective blocks using the initial layout result;
• (c) code that calculates tan-out capacitance limitation values of the respective blocks using the wiring capacitance values of the blocks calculated in the step (b);
• each of the fan-out capacitance limitation values representing a maximum fan-out capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or leas than a specific limitation value;
• (d) code that compares a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
• (e) code that defines the blocks whose driving capabilities do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result;
• and
• (f) code that changes circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.

A computer program product having a computer readable medium and a computer program recorded thereon, the computer program being operable to perform a method of performing timing-driven layout of a circuit, the product comprising:

• (a) code that generates an initial layout result through placement of functional blocks of the circuit;
• (b) code that estimates wiring capacitance values of the respective blocks using the initial layout result;
• (c) code that calculates fan-out capacitance limitation values for the respective blocks using the wiring capacitance values of the blocks estimated in the step (b);
• each of the fan-out capacitance limitation values representing a maximum capacitance value of a corresponding one of the blocks at which wiring-induced propagation delay of the block is equal to or less than a specific limitation value;
• (d) code that compares a driving capability of each of the blocks with its fan-out capacitance limitation value, thereby generating a comparison result;
• (e) code that defines the blocks whose wiring capacitance values do not exceed their fan-out capacitance limitation values as timing-error blocks based on the comparison result;
• and
• (f) code that changes circuit configuration of each of the timing-error blocks based on its fan-out capacitance limitation value to decrease its propagation delay.