Fast method of I/O circuit placement and electrical rule checking
AssigneeInternational Business Machines Corporation
InventorsCharles S. Chiu, James P. Libous, Rory D. Loughran, Joseph Natonio, Robert A. Proctor, Gulsun Yasar
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Abstract
A method of analyzing I/O cell layouts for integrated circuits, such as ASICs, includes defining a proposed I/O cell layout on a selected chip image, providing a set of limit rules for electromigration, IR voltage drop and di/dt noise for the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the limit rules to the proposed I/O cell layout and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.
Claims20
A method of analyzing I/O cell layouts for integrated circuits, the method comprising the steps of:
- providing data defining a proposed I/O cell layout for a plurality of I/O cells;
- providing a set of limit rules for a selected chip image, the limit rules defining limits on the layout of I/O cells on the selected chip image;
- providing characteristics for each I/O cell type used in the proposed I/O cell layout;
- checking the proposed I/O cell layout using a fast circuit solver by applying the data defining the proposed I/O cell layout and the characteristics for each I/O cell type used in the proposed I/O cell layout to the set of limit rules;
- and
- reporting all I/O cells in the proposed I/O cell layout that do not meet the set of limit rules for the selected chip image.
A method of checking I/O cell placement for IR drop and noise for a peripheral chip image, the method comprising the steps of:
- proposing an I/O cell layout containing duty cycle, switch factor and load termination at which each I/O cell will operate at;
- creating a set of rules for the I/O cells and the chip image;
- applying the rules to each of the I/O cells for duty cycle, switch factor and load termination;
- checking the proposed an I/O cell layout against the set of rules using a fast circuit solver;
- and
- reporting the IR drop and noise characteristics of the chip image as indicated after the application of the rules.
Dependencies are inferred from the claim text.