Apparatus and method of layout generation, and program thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakashi Fujii
Life of this patent
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Abstract
A layout generating apparatus and a layout generating method to obtain high-quality optimization results (improvements in operation speed and the degree of integration and a reduction in power consumption). Specifically, there are disposed input data storage part (1), before-compaction layout generating part (2), first compaction processing part (3), second compaction processing part (4), third compaction processing part (5), mid-course-processing data storage part (6), channel-width optimization processing part (7), layout optimization processing part (8), output data storage part (9), and control part (10). The operations of all the mentioned parts are controlled by the control part (10).
Claims11
A layout generating apparatus to generate a layout of a semiconductor integrated circuit, comprising:
- a compaction processing part to perform a compaction processing for converting an inputted input layout into a layout satisfying a predetermined design rule;
- and
- a channel-width optimization processing part to optimize a channel width of a transistor forming said semiconductor integrated circuit,
- said compaction processing part having
- a channel-width maximization processing part that maximizes the channel width of said transistor without changing a layout area to generate a layout after channel-width maximization and obtain a maximum channel-width value,
- said channel-width optimization processing part optimizing the channel width of said transistor by using said maximum channel-width value as an upper limit value.
A layout generating method of generating a layout of a semiconductor integrated circuit comprising the steps of:
- (a) performing a compaction processing for converting an inputted input layout into a layout satisfying a predetermined design rule;
- and
- (b) optimizing the channel width of a transistor forming said semiconductor integrated circuit,
- said step (a) including:
- (a-1) maximizing the channel width of said transistor without changing a layout area to obtain a layout after channel-width maximization;
- and
- (a-2) obtaining a maximum channel-width value from said layout after channel-width maximization,
- said step (b) including the step of:
- optimizing the channel width of said transistor by using said maximum channel-width value as an upper limit value.
Dependencies are inferred from the claim text.