Method of designing a voltage partitioned solder-bump package
AssigneeInternational Business Machines Corporation
InventorsPatrick H. Buffet, Charles S. Chiu, Yu H. Sun
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Abstract
Disclosed is a method of designing voltage partitions in a solder bump package for a chip, comprising: determining the current requirements of a chip voltage island, the chip voltage island including chip power and signal pads, and creating an equivalent circuit model of the chip voltage island; defining a package voltage island, the package voltage island including power and signal package pins, and creating an equivalent circuit model of the package voltage island; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model; and modifying the package voltage island until the electrical attributes are acceptable.
Claims36
A method of designing voltage partitions in a solder bump package for a chip, comprising:
- determining the current requirements of a chip voltage island, said chip voltage island including chip power and signal pads, and creating an equivalent circuit model of said chip voltage island;
- defining a package voltage island, said package voltage island including power and signal package pins, and creating an equivalent circuit model of said package voltage island;
- analyzing electrical attributes of a combination of said chip voltage island model and said package voltage island model;
- and modifying said package voltage island until said electrical attributes are acceptable.
A computer system comprising a processor, an address/data bus coupled to said processor, and a computer-readable memory unit coupled to communicate with said processor, said memory unit containing instructions that when executed implement a method for designing voltage partitions in a package for a chip, said method comprising the computer implemented steps of:
- determining the current requirements of a chip voltage island, said chip voltage island including chip power and signal pads, and creating an equivalent circuit model of said chip voltage island;
- defining a package voltage island, said package voltage island including power and signal package pins, and creating an equivalent circuit model of said package voltage island;
- analyzing electrical attributes of a combination of said chip voltage island model and said package voltage island model;
- and modifying said package voltage island until said electrical attributes are acceptable.
A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for designing voltage partitions in a package for a chip said method steps comprising:
- determining the current requirements of a chip voltage island, said chip voltage island including chip power and signal pads, and creating an equivalent circuit model of said chip voltage island;
- defining a package voltage island, said package voltage island including power and signal package pins, and creating an equivalent circuit model of said package voltage island;
- analyzing electrical attributes of a combination of said chip voltage island model and said package voltage island model;
- and modifying said package voltage island until said electrical attributes are acceptable.
Dependencies are inferred from the claim text.