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US 6,584,594 B1Granted
Data pre-reading and error correction circuit for a memory device
AssigneeAdvanced Micro Devices, Inc.
InventorDonald Monroe Walters, Jr.
Life of this patent
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Abstract
A circuit for correction of errors in a memory device comprises a data word byte counter 16, data encoders 18 and 20, a syndrome accumulator 22, a data word byte address generator 24, a comparator 26, a decoder 28 and an error correction enable buffer 30. The error correction circuit 4 is coupled to a memory array 2 through a pre-read input-output bus 14, and is further coupled to an input-output multiplexer buffer 6 which is coupled between the memory array 2 and a data bus 12.
Claims99
An error correction circuit for a memory device, comprising:
- (a) a data word byte counter;
- (b) first and second data encoders capable of receiving first and second pre-read data bytes, respectively;
- (c) a syndrome accumulator, coupled to the data word byte counter and the first and second data encoders, capable of generating a syndrome comprising first and second pluralities of syndrome bits;
- (d) a data word byte address generator, coupled to the syndrome generator, capable of generating a plurality of data word byte address bits;
- (e) a comparator, coupled to the syndrome accumulator and the data word byte address generator, capable of generating an error correction enable signal in response to comparing the first plurality of the syndrome bits with the data word byte address bits;
- (f) a decoder, coupled to the syndrome accumulator, capable of decoding the second plurality of the syndrome bits to generate a plurality of decoded data input bits;
- and
- (g) a correction enable buffer, coupled to the comparator and the decoder, capable of generating a plurality of correction bits in response to receiving the decoded data input bits and the error correction enable signal.
5 more elements
A memory device, comprising:
- (a) a memory array;
- (b) an error correction circuit, coupled to the memory array, comprising:
- (i) a data word byte counter;
- (ii) first and second data encoders capable of receiving first and second pre-read data bytes, respectively;
- (iii) a syndrome accumulator, coupled to the data word byte counter and the first and second data encoders, capable of generating a syndrome comprising first and second pluralities of syndrome bits;
- (iv) a data word byte address generator, coupled to the syndrome generator, capable of generating a plurality of data word byte address bits;
- (v) a comparator, coupled to the syndrome accumulator and the data word byte address generator, capable of generating an error correction enable signal in response to comparing the first plurality of the syndrome bits with the data word byte address bits;
- (vi) a decoder, coupled to the syndrome accumulator, capable of decoding the second plurality of the syndrome bits to generate a plurality of decoded data input bits;
- and
- (vii) a correction enable buffer, coupled to the comparator and the decoder, capable of generating a plurality of correction bits in response to receiving the decoded data input bits and the error correction enable signal;
- and
- (c) an input-output multiplexer buffer coupled to the memory array and to the correction enable buffer.
9 more elements
An error correction circuit for a memory device, comprising:
- (a) a data word byte counter;
- (b) first and second data encoders capable of receiving first and second pre-read data bytes, respectively;
- (c) a multiplexer coupled to the second data encoder;
- (d) a syndrome accumulator, coupled to the data word byte counter and the first and second data encoders, capable of generating a syndrome comprising first and second pluralities of syndrome bits;
- (e) a syndrome latch, coupled between the syndrome accumulator and the multiplexer, to store the first and second pluralities of the syndrome bits;
- (f) a data word byte address generator, coupled to the syndrome accumulator, capable of generating a plurality of data word byte address bits;
- (g) a comparator, coupled to the syndrome latch and the data word byte address generator, capable of generating an error correction enable signal in response to comparing the first plurality of the syndrome bits with the data word byte address bits;
- (h) a decoder, coupled to the syndrome latch, capable of decoding the second plurality of the syndrome bits to generate a plurality of decoded data input bits;
- and
- (i) a correction enable buffer, coupled to the comparator and the decoder, capable of generating a plurality of correction bits in response to receiving the decoded data input bits and the error correction enable signal.
7 more elements
A memory device, comprising:
- (a) a memory array;
- (b) an error correction circuit, coupled to the memory array, comprising:
- (i) a data word byte counter;
- (ii) first and second data encoders capable of receiving first and second pre-read data bytes, respectively;
- (iii) a multiplexer coupled to the second data encoder;
- (iv) a syndrome accumulator, coupled to the data word byte counter and the first and second data encoders, capable of generating a syndrome comprising first and second pluralities of syndrome bits;
- (v) a syndrome latch, coupled between the syndrome accumulator and the multiplexer, to store the first and second pluralities of the syndrome bits;
- (vi) a data word byte address generator, coupled to the syndrome generator, capable of generating a plurality of data word byte address bits;
- (vii) a comparator, coupled to the syndrome latch and the data word byte address generator, capable of generating an error correction enable signal in response to comparing the first plurality of the syndrome bits with the data word byte address bits;
- (viii) a decoder, coupled to the syndrome latch, capable of decoding the second plurality of the syndrome bits to generate a plurality of decoded data input bits;
- and
- (ix) a correction enable buffer, coupled to the comparator and the decoder, capable of generating a plurality of correction bits in response to receiving the decoded data input bits and the error correction enable signal;
- and
- (c) an input-output multiplexer buffer coupled to the memory array and to the correction enable buffer.
11 more elements
Dependencies are inferred from the claim text.