Semiconductor testing apparatus for testing semiconductor device including built in self test circuit
AssigneesMitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System
InventorsRyuji Omura, Kazushi Sugiura, Mari Shibayama
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Abstract
A program power supply of a tester applies a power supply voltage to an IC to be tested. A pattern generator applies a clock signal and a command signal to a BIST circuit of IC. BIST circuit tests memory IC unit and logic IC unit and serially outputs data indicative of test result to a converter of tester. Converter converts the applied serial data to parallel data and applies to computer. As compared with the prior art in which address signal and control signal are applied to IC to be tested, the number of pins necessary for the test can be reduced. Therefore, cost of the test is reduced and efficiency of the test is improved.
Claims8
A method of testing a semiconductor device including a memory circuit having a plurality of memory cells, and a built-in self test circuit, said method comprising:
- the first step of applying an external power supply voltage to said semiconductor device;
- the second step of applying a first external command signal to said semiconductor device to have a built-in self test circuit test said memory circuit, said built-in self test circuit performing a test to determine whether each of the memory cells in the memory circuit is normal or not;
- and
- the third step of applying a second external command signal to said semiconductor device to have said built-in self test circuit externally output data representing a result of the test and receiving the data.
Dependencies are inferred from the claim text.