Timing control for input/output testability

#1. Field of the Invention

#The invention is related to source synchronous techniques, and in particular to the addition of delay circuitry to a chip that uses source synchronous techniques to improve testability of the chip.

#2. Description of the Related Art

#Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

#FIG. 1 is a timing representation of coincident and centered clocking for source synchronous data transfer;

#FIG. 2a is a representation of a typical coincident clocking transmitter/receiver (DLL) system;

#While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

#Illustrative embodiments of the invention are described below as they might be employed in a chip or multi-chip system using source synchronous techniques. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

#Referring to the drawings, and specifically to FIG. 3, in accordance with an embodiment of the invention, a portion 51 of a DLL 32″, which is a modification of the DLL 32 in FIG. 2a (or DLL 32′ in FIG. 2b), is illustrated. The modified portion 51 generates a control voltage Vcntl 50b″ for the delay lines 36 and 42 that permits additional controllability of the delay lines 36 and 42. Not all details of the DLL 32″ are shown in FIG. 3, and only the portion 51 of the DLL 32″ is shown for simplification of the drawings. It is to be understood, however, that the other elements of the DLL 32 (or DLL 32′) shown in FIG. 2a (or FIG. 2b) are also included in the DLL 32″. In the DLL 32″, a pass gate multiplexer 60, whose output is a signal 50a″, is added between the PD 48 and the RC low pass filter 52. The signal 50a″ is converted to the control voltage Vcntl 50b″ (which will be, in general, different for the DLL 32′ and the DLL 32 because of the differences discussed above related to their respective lack of and inclusion of the RC distribution networks). The multiplexer 60 allows Vcntl 50b″ to be alternatively driven from a digital-to-analog converter (DAC) 62. The delay of the DLL 32″ may be controlled accordingly by the PD 48 in normal operation, or externally controlled (e.g., by a logic tester [not shown]) during testing, when so enabled by a “test” signal 61 to the multiplexer 60. The PD 48 drives the RC low pass filter 52 if test signal 61 is not enabled, and ideally provides a 90 degree phase shift between the strobe 14 and the DlyStb 40 or 40″ signals (see FIGS. 2a-b) for coincident clocking or centered clocking. (The signal 40″ is not, in general, the same as the DlyStb 40 signal because the DLL 32″ [FIG. 3], whose operation results in a signal 40′ [≅14′], lacks the RC distribution network 38′.) External control with the logic tester allows the time to be varied at which the delayed strobe signal, DlyStb 40 or 40″ (i.e., the signal after the RC distribution network 38′), reaches the data latch 34. The DAC 62 provides an input value to the filter 52 that adjusts the delay of the DlyStb 40 (or 40″) signal by modifying Vcntl 50b″.