Self-testing of magneto-resistive memory arrays

A built-in self testing system for a magneto-resistive random access memory (MRAM) integrated circuit having an array of memory cells, the memory cells each coupled between a respective row line and column line of the array, with sense amplifiers being coupled to the column lines of the array to sense data stored in the memory cells and a scan register coupled to receive output from the sense amplifiers and provide input for the memory cells in the array, the built-in self-testing system comprising:

• a first testing circuit comprising a resistance specification testing circuit coupled to the respective sense amplifiers for testing the resistance of each memory cell in the memory array to determine if the resistance thereof is within predetermined upper and lower limits;
• a second testing circuit coupled to the row lines of the memory array for detecting shorted memory cells and open row addressing lines in the respective array rows;
• and
• a third testing circuit coupled to the scan register of the memory array and arranged to write a predetermined data pattern into the memory array, read out data from the memory array, and compare the data read out with the data written in.

A method for providing a built-in self testing capability for a magneto-resistive random access memory (MRAM) integrated circuit having an array of memory cells with at least one sense amplifier for sensing data stored in the memory cells, comprising:

• using the sense amplifier to generate a current signal representing a sensing current through a memory cell in the array;
• time integrating the current signal and applying a threshold thereto to produce a binary output;
• sampling the binary output at first and second times;
• and
• registering the memory cell as outside predetermined resistance specifications based on the first and second sampled binary outputs.