Processor and multiprocessor system
AssigneeHitachi, Ltd.
InventorsAkihiro Yamato, Kei Yamamoto
Life of this patent
Estimating the term…
Abstract
For use in a multiprocessor system in which a plurality of processors share a main memory via a processor bus, an error processing unit (EU) that determines an error level is provided in each processor. When an L2 cache control unit (SU) that controls an L2 cache in the write-back mode, a bus interface unit (PU), and so on, are normal and snoop processing may be continued, the snoop processing is continued in the processor, in which an error occurred, regardless of whether or not the processor is reset. This prevents the system from going down even when data coherence among L2 caches is lost due to an error that occurs in one of processors.
Claims9
A processor including a processing unit which issues an instruction and performs operation, a memory control unit which controls a cache memory containing a copy of data stored in a main memory, and a snoop processing unit which, when said main memory is shared with other processors, performs snoop processing to make contents of cache memories coherent, each of said cache memories being controlled by the processor and by each of the other processors, said processor comprising:
- an error determination unit which checks, when an error occurs in the processor disabling an instruction execution, if said snoop processing can be performed;
- and
- a control unit which continues said snoop processing if, as a result of said checking, said snoop processing can be performed.
A multiprocessor system comprising a main memory, a plurality of processors sharing said main memory, and a bus connecting said main memory and said plurality of processors, each of said plurality of processors comprising:
- a processing unit which issues an instruction and performs operation;
- a cache memory containing a copy of data stored in said main memory;
- a memory control unit which controls said cache memory;
- a snoop processing unit which performs snoop processing to make contents of cache memories coherent, each of said cache memories being provided in the processor and each of other processors;
- an error determination unit which checks, when an error occurs in the processor disabling an instruction execution, if said snoop processing can be performed;
- and
- a control unit which continues said snoop processing if, as a result of said checking, said snoop processing can be performed.
A processor including an operation logic unit which performs data processing, a cache memory temporarily storing therein data which is generated by said operation logic unit and which is to be stored into a main memory, and a snoop processing logic which, when said main memory is shared with other processors, performs snoop processing to make contents of each said cache memory logically consistent among the processors, comprising:
- an error determination logic which checks if said snoop processing can be performed when an error occurs in said processor disabling an instruction execution;
- and
- a control logic which performs a reset operation of said processor while continuing said snoop processing if said snoop processing can be performed when the error occurs in said processor.
Dependencies are inferred from the claim text.