Arbitration method and circuit for control of integrated circuit double data rate (DDR) memory device output first-in, first-out (FIFO) registers

A circuit for generating a data sort clock signal from an input system clock and delay locked loop clock signals, said circuit comprising:

• first, second, third and fourth series connected switching devices having a respective control terminal thereof;
• said delay locked loop clock signal being coupled to said control terminal of said first and fourth switching devices and said system clock signal being coupled to said control terminal of said second switching device;
• a delay circuit coupled to receive said delay locked loop clock signal for providing a delayed delay locked loop clock signal to said control terminal of said third switching device;
• and
• a latch circuit coupled intermediate said first and second switching devices for providing said data sort clock signal.

An integrated circuit memory device comprising:

• a system clock signal and a derivative delay clock signal, wherein said derivative delay clock signal runs either ahead of or behind said system clock;
• a data sort clock circuit coupled to receive said system clock signal and said delay clock signal to provide a data sort clock signal;
• and
• at least one data path selectively enablable by said system clock signal, said delay clock signal and said data sort clock signal.

A method for associating a first clock signal with a second derivative clock signal comprising:

• determining an overlap between said first and second clock signals;
• comparing said determined overlap with a predetermined overlap limit;
• considering said second clock signal to be faster than said first clock signal if said determined overlap is less than said predetermined overlap limit;
• and
• utilizing said second clock signal to clock data through an integrated circuit device.

An arbitration circuit for associating a first clock signal with a second derivative clock signal in an integrated circuit memory device, said circuit comprising:

• means for determining an overlap between said first and second clock signals;
• means for comparing said determined overlap with a predetermined overlap limit;
• means for considering said second clock signal to be faster than said first clock signal if said determined overlap is less than said predetermined overlap limit;
• and
• means for utilizing said second clock signal to clock data through an integrated circuit device.